
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version   : 0.4.1
// timestamp : Wed Dec 16 03:37:04 2020 GMT
// usage     : riscv_ctg \
//                  -- cgf ('/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/dataset.cgf', '/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/rv32ic.cgf') \
//                  -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.addi4spn instruction of the RISC-V C extension for the caddi4spn covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IC")

.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*C.*);def TEST_CASE_1=True;",caddi4spn)

RVTEST_SIGBASE( x1,signature_x1_1)

inst_0:
// rd==x14, imm_val > 0, 
// opcode:c.addi4spn; dest:x14; immval:0x1c
TEST_CADDI4SPN_OP( c.addi4spn, x14, 0x1c, 0x1c, x1, 0, x2)

inst_1:
// rd==x8, imm_val == 1020, 
// opcode:c.addi4spn; dest:x8; immval:0x3fc
TEST_CADDI4SPN_OP( c.addi4spn, x8, 0x3fc, 0x3fc, x1, 4, x2)

inst_2:
// rd==x9, imm_val == 4, 
// opcode:c.addi4spn; dest:x9; immval:0x4
TEST_CADDI4SPN_OP( c.addi4spn, x9, 0x4, 0x4, x1, 8, x2)

inst_3:
// rd==x15, imm_val == 8, 
// opcode:c.addi4spn; dest:x15; immval:0x8
TEST_CADDI4SPN_OP( c.addi4spn, x15, 0x8, 0x8, x1, 12, x2)

inst_4:
// rd==x10, imm_val == 16, 
// opcode:c.addi4spn; dest:x10; immval:0x10
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x10, 0x10, x1, 16, x2)

inst_5:
// rd==x12, imm_val == 32, 
// opcode:c.addi4spn; dest:x12; immval:0x20
TEST_CADDI4SPN_OP( c.addi4spn, x12, 0x20, 0x20, x1, 20, x2)

inst_6:
// rd==x11, imm_val == 64, 
// opcode:c.addi4spn; dest:x11; immval:0x40
TEST_CADDI4SPN_OP( c.addi4spn, x11, 0x40, 0x40, x1, 24, x2)

inst_7:
// rd==x13, imm_val == 128, 
// opcode:c.addi4spn; dest:x13; immval:0x80
TEST_CADDI4SPN_OP( c.addi4spn, x13, 0x80, 0x80, x1, 28, x2)

inst_8:
// imm_val == 256, 
// opcode:c.addi4spn; dest:x10; immval:0x100
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x100, 0x100, x1, 32, x2)

inst_9:
// imm_val == 512, 
// opcode:c.addi4spn; dest:x10; immval:0x200
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x200, 0x200, x1, 36, x2)

inst_10:
// imm_val == 1016, 
// opcode:c.addi4spn; dest:x10; immval:0x3f8
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x3f8, 0x3f8, x1, 40, x2)

inst_11:
// imm_val == 1012, 
// opcode:c.addi4spn; dest:x10; immval:0x3f4
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x3f4, 0x3f4, x1, 44, x2)

inst_12:
// imm_val == 1004, 
// opcode:c.addi4spn; dest:x10; immval:0x3ec
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x3ec, 0x3ec, x1, 48, x2)

inst_13:
// imm_val == 764, 
// opcode:c.addi4spn; dest:x10; immval:0x2fc
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x2fc, 0x2fc, x1, 52, x2)

inst_14:
// imm_val == 508, 
// opcode:c.addi4spn; dest:x10; immval:0x1fc
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x1fc, 0x1fc, x1, 56, x2)

inst_15:
// imm_val == 340, 
// opcode:c.addi4spn; dest:x10; immval:0x154
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x154, 0x154, x1, 60, x2)

inst_16:
// imm_val == 680, 
// opcode:c.addi4spn; dest:x10; immval:0x2a8
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x2a8, 0x2a8, x1, 64, x2)

inst_17:
// imm_val == 988, 
// opcode:c.addi4spn; dest:x10; immval:0x3dc
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x3dc, 0x3dc, x1, 68, x2)

inst_18:
// imm_val == 956, 
// opcode:c.addi4spn; dest:x10; immval:0x3bc
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x3bc, 0x3bc, x1, 72, x2)

inst_19:
// imm_val == 892, 
// opcode:c.addi4spn; dest:x10; immval:0x37c
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x37c, 0x37c, x1, 76, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4

rvtest_data:
.word 0xbabecafe
.word 0xbabecafe
.word 0xbabecafe
.word 0xbabecafe
RVTEST_DATA_END


RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x1_1:
    .fill 20*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
