// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version   : 0.5.1
// timestamp : Wed Aug  4 06:39:00 2021 GMT
// usage     : riscv_ctg \
//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
//                  --base-isa rv32e \
//                  --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.lwsp instruction of the RISC-V C extension for the clwsp covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",clwsp)

RVTEST_SIGBASE( x5,signature_x5_1)

inst_0:
// rd==x2, imm_val == 0, 
// opcode: c.lwsp; op1:x2; dest:x2; immval:0x0
TEST_LOAD(x5,x7,0,x2,x2,0x0,0,c.lwsp,0)

inst_1:
// rd==x11, imm_val == 124, imm_val > 0
// opcode: c.lwsp; op1:x2; dest:x11; immval:0x7c
TEST_LOAD(x5,x7,0,x2,x11,0x7c,4,c.lwsp,0)

inst_2:
// rd==x3, imm_val == 188, 
// opcode: c.lwsp; op1:x2; dest:x3; immval:0xbc
TEST_LOAD(x5,x7,0,x2,x3,0xbc,8,c.lwsp,0)

inst_3:
// rd==x6, imm_val == 220, 
// opcode: c.lwsp; op1:x2; dest:x6; immval:0xdc
TEST_LOAD(x5,x7,0,x2,x6,0xdc,12,c.lwsp,0)

inst_4:
// rd==x9, imm_val == 236, 
// opcode: c.lwsp; op1:x2; dest:x9; immval:0xec
TEST_LOAD(x5,x7,0,x2,x9,0xec,16,c.lwsp,0)

inst_5:
// rd==x1, imm_val == 244, 
// opcode: c.lwsp; op1:x2; dest:x1; immval:0xf4
TEST_LOAD(x5,x7,0,x2,x1,0xf4,20,c.lwsp,0)

inst_6:
// rd==x4, imm_val == 248, 
// opcode: c.lwsp; op1:x2; dest:x4; immval:0xf8
TEST_LOAD(x5,x7,0,x2,x4,0xf8,24,c.lwsp,0)

inst_7:
// rd==x8, imm_val == 128, 
// opcode: c.lwsp; op1:x2; dest:x8; immval:0x80
TEST_LOAD(x5,x7,0,x2,x8,0x80,28,c.lwsp,0)

inst_8:
// rd==x15, imm_val == 64, 
// opcode: c.lwsp; op1:x2; dest:x15; immval:0x40
TEST_LOAD(x5,x7,0,x2,x15,0x40,32,c.lwsp,0)

inst_9:
// rd==x12, imm_val == 32, 
// opcode: c.lwsp; op1:x2; dest:x12; immval:0x20
TEST_LOAD(x5,x7,0,x2,x12,0x20,36,c.lwsp,0)

inst_10:
// rd==x10, imm_val == 16, 
// opcode: c.lwsp; op1:x2; dest:x10; immval:0x10
TEST_LOAD(x5,x7,0,x2,x10,0x10,40,c.lwsp,0)

inst_11:
// rd==x14, imm_val == 8, 
// opcode: c.lwsp; op1:x2; dest:x14; immval:0x8
TEST_LOAD(x5,x3,0,x2,x14,0x8,44,c.lwsp,0)
RVTEST_SIGBASE( x1,signature_x1_0)

inst_12:
// rd==x13, imm_val == 4, 
// opcode: c.lwsp; op1:x2; dest:x13; immval:0x4
TEST_LOAD(x1,x3,0,x2,x13,0x4,0,c.lwsp,0)

inst_13:
// rd==x5, imm_val == 168, 
// opcode: c.lwsp; op1:x2; dest:x5; immval:0xa8
TEST_LOAD(x1,x3,0,x2,x5,0xa8,4,c.lwsp,0)

inst_14:
// rd==x7, imm_val == 84, 
// opcode: c.lwsp; op1:x2; dest:x7; immval:0x54
TEST_LOAD(x1,x3,0,x2,x7,0x54,8,c.lwsp,0)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4

rvtest_data:
.word 0xbabecafe
.word 0xbabecafe
.word 0xbabecafe
.word 0xbabecafe
RVTEST_DATA_END


RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x5_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x5_1:
    .fill 12*(XLEN/32),4,0xdeadbeef


signature_x1_0:
    .fill 3*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
