
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Sun Aug  7 17:43:57 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/anku/work2/bmanip/32/dataset.yaml \
//                  --cgf /home/anku/work2/bmanip/32/rv32ib.yaml \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the clmulr instruction of the RISC-V RV32Zbc extension for the clmulr covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IZbc")

.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*Zbc.*);def TEST_CASE_1=True;",clmulr)

RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 == rs2 == rd, rs1==x31, rs2==x31, rd==x31, 
// opcode: clmulr ; op1:x31; op2:x31; dest:x31; op1val:0x0;  op2val:0x0
TEST_RR_OP(clmulr, x31, x31, x31, 0x00000000, 0x0, 0x0, x1, 0, x2)

inst_1:
// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x29, rs2==x28, rd==x30, 
// opcode: clmulr ; op1:x29; op2:x28; dest:x30; op1val:0xffffffff;  op2val:0x7fffffff
TEST_RR_OP(clmulr, x30, x29, x28, 0x00000000, 0xffffffff, 0x7fffffff, x1, 4, x2)

inst_2:
// rs1 == rd != rs2, rs1==x28, rs2==x30, rd==x28, 
// opcode: clmulr ; op1:x28; op2:x30; dest:x28; op1val:0xffffffff;  op2val:0xbfffffff
TEST_RR_OP(clmulr, x28, x28, x30, 0x00000000, 0xffffffff, 0xbfffffff, x1, 8, x2)

inst_3:
// rs1 == rs2 != rd, rs1==x27, rs2==x27, rd==x29, 
// opcode: clmulr ; op1:x27; op2:x27; dest:x29; op1val:0xffffffff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x29, x27, x27, 0x00000000, 0xffffffff, 0xffffffff, x1, 12, x2)

inst_4:
// rs2 == rd != rs1, rs1==x30, rs2==x26, rd==x26, 
// opcode: clmulr ; op1:x30; op2:x26; dest:x26; op1val:0xffffffff;  op2val:0xefffffff
TEST_RR_OP(clmulr, x26, x30, x26, 0x00000000, 0xffffffff, 0xefffffff, x1, 16, x2)

inst_5:
// rs1==x26, rs2==x29, rd==x27, 
// opcode: clmulr ; op1:x26; op2:x29; dest:x27; op1val:0xffffffff;  op2val:0xf7ffffff
TEST_RR_OP(clmulr, x27, x26, x29, 0x00000000, 0xffffffff, 0xf7ffffff, x1, 20, x2)

inst_6:
// rs1==x24, rs2==x23, rd==x25, 
// opcode: clmulr ; op1:x24; op2:x23; dest:x25; op1val:0xffffffff;  op2val:0xfbffffff
TEST_RR_OP(clmulr, x25, x24, x23, 0x00000000, 0xffffffff, 0xfbffffff, x1, 24, x2)

inst_7:
// rs1==x23, rs2==x25, rd==x24, 
// opcode: clmulr ; op1:x23; op2:x25; dest:x24; op1val:0xffffffff;  op2val:0xfdffffff
TEST_RR_OP(clmulr, x24, x23, x25, 0x00000000, 0xffffffff, 0xfdffffff, x1, 28, x2)

inst_8:
// rs1==x25, rs2==x24, rd==x23, 
// opcode: clmulr ; op1:x25; op2:x24; dest:x23; op1val:0xffffffff;  op2val:0xfeffffff
TEST_RR_OP(clmulr, x23, x25, x24, 0x00000000, 0xffffffff, 0xfeffffff, x1, 32, x2)

inst_9:
// rs1==x21, rs2==x20, rd==x22, 
// opcode: clmulr ; op1:x21; op2:x20; dest:x22; op1val:0xffffffff;  op2val:0xff7fffff
TEST_RR_OP(clmulr, x22, x21, x20, 0x00000000, 0xffffffff, 0xff7fffff, x1, 36, x2)

inst_10:
// rs1==x20, rs2==x22, rd==x21, 
// opcode: clmulr ; op1:x20; op2:x22; dest:x21; op1val:0xffffffff;  op2val:0xffbfffff
TEST_RR_OP(clmulr, x21, x20, x22, 0x00000000, 0xffffffff, 0xffbfffff, x1, 40, x2)

inst_11:
// rs1==x22, rs2==x21, rd==x20, 
// opcode: clmulr ; op1:x22; op2:x21; dest:x20; op1val:0xffffffff;  op2val:0xffdfffff
TEST_RR_OP(clmulr, x20, x22, x21, 0x00000000, 0xffffffff, 0xffdfffff, x1, 44, x2)

inst_12:
// rs1==x18, rs2==x17, rd==x19, 
// opcode: clmulr ; op1:x18; op2:x17; dest:x19; op1val:0xffffffff;  op2val:0xffefffff
TEST_RR_OP(clmulr, x19, x18, x17, 0x00000000, 0xffffffff, 0xffefffff, x1, 48, x2)

inst_13:
// rs1==x17, rs2==x19, rd==x18, 
// opcode: clmulr ; op1:x17; op2:x19; dest:x18; op1val:0xffffffff;  op2val:0xfff7ffff
TEST_RR_OP(clmulr, x18, x17, x19, 0x00000000, 0xffffffff, 0xfff7ffff, x1, 52, x2)

inst_14:
// rs1==x19, rs2==x18, rd==x17, 
// opcode: clmulr ; op1:x19; op2:x18; dest:x17; op1val:0xffffffff;  op2val:0xfffbffff
TEST_RR_OP(clmulr, x17, x19, x18, 0x00000000, 0xffffffff, 0xfffbffff, x1, 56, x2)

inst_15:
// rs1==x15, rs2==x14, rd==x16, 
// opcode: clmulr ; op1:x15; op2:x14; dest:x16; op1val:0xffffffff;  op2val:0xfffdffff
TEST_RR_OP(clmulr, x16, x15, x14, 0x00000000, 0xffffffff, 0xfffdffff, x1, 60, x2)

inst_16:
// rs1==x14, rs2==x16, rd==x15, 
// opcode: clmulr ; op1:x14; op2:x16; dest:x15; op1val:0xffffffff;  op2val:0xfffeffff
TEST_RR_OP(clmulr, x15, x14, x16, 0x00000000, 0xffffffff, 0xfffeffff, x1, 64, x2)

inst_17:
// rs1==x16, rs2==x15, rd==x14, 
// opcode: clmulr ; op1:x16; op2:x15; dest:x14; op1val:0xffffffff;  op2val:0xffff7fff
TEST_RR_OP(clmulr, x14, x16, x15, 0x00000000, 0xffffffff, 0xffff7fff, x1, 68, x2)

inst_18:
// rs1==x12, rs2==x11, rd==x13, 
// opcode: clmulr ; op1:x12; op2:x11; dest:x13; op1val:0xffffffff;  op2val:0xffffbfff
TEST_RR_OP(clmulr, x13, x12, x11, 0x00000000, 0xffffffff, 0xffffbfff, x1, 72, x2)

inst_19:
// rs1==x11, rs2==x13, rd==x12, 
// opcode: clmulr ; op1:x11; op2:x13; dest:x12; op1val:0xffffffff;  op2val:0xffffdfff
TEST_RR_OP(clmulr, x12, x11, x13, 0x00000000, 0xffffffff, 0xffffdfff, x1, 76, x2)

inst_20:
// rs1==x13, rs2==x12, rd==x11, 
// opcode: clmulr ; op1:x13; op2:x12; dest:x11; op1val:0xffffffff;  op2val:0xffffefff
TEST_RR_OP(clmulr, x11, x13, x12, 0x00000000, 0xffffffff, 0xffffefff, x1, 80, x2)

inst_21:
// rs1==x9, rs2==x8, rd==x10, 
// opcode: clmulr ; op1:x9; op2:x8; dest:x10; op1val:0xffffffff;  op2val:0xfffff7ff
TEST_RR_OP(clmulr, x10, x9, x8, 0x00000000, 0xffffffff, 0xfffff7ff, x1, 84, x2)

inst_22:
// rs1==x8, rs2==x10, rd==x9, 
// opcode: clmulr ; op1:x8; op2:x10; dest:x9; op1val:0xffffffff;  op2val:0xfffffbff
TEST_RR_OP(clmulr, x9, x8, x10, 0x00000000, 0xffffffff, 0xfffffbff, x1, 88, x2)

inst_23:
// rs1==x10, rs2==x9, rd==x8, 
// opcode: clmulr ; op1:x10; op2:x9; dest:x8; op1val:0xffffffff;  op2val:0xfffffdff
TEST_RR_OP(clmulr, x8, x10, x9, 0x00000000, 0xffffffff, 0xfffffdff, x1, 92, x2)

inst_24:
// rs1==x6, rs2==x5, rd==x7, 
// opcode: clmulr ; op1:x6; op2:x5; dest:x7; op1val:0xffffffff;  op2val:0xfffffeff
TEST_RR_OP(clmulr, x7, x6, x5, 0x00000000, 0xffffffff, 0xfffffeff, x1, 96, x2)
RVTEST_SIGBASE(x8,signature_x8_0)

inst_25:
// rs1==x5, rs2==x7, rd==x6, 
// opcode: clmulr ; op1:x5; op2:x7; dest:x6; op1val:0xffffffff;  op2val:0xffffff7f
TEST_RR_OP(clmulr, x6, x5, x7, 0x00000000, 0xffffffff, 0xffffff7f, x8, 0, x9)

inst_26:
// rs1==x7, rs2==x6, rd==x5, 
// opcode: clmulr ; op1:x7; op2:x6; dest:x5; op1val:0xffffffff;  op2val:0xffffffbf
TEST_RR_OP(clmulr, x5, x7, x6, 0x00000000, 0xffffffff, 0xffffffbf, x8, 4, x9)

inst_27:
// rs1==x3, rs2==x2, rd==x4, 
// opcode: clmulr ; op1:x3; op2:x2; dest:x4; op1val:0xffffffff;  op2val:0xffffffdf
TEST_RR_OP(clmulr, x4, x3, x2, 0x00000000, 0xffffffff, 0xffffffdf, x8, 8, x9)

inst_28:
// rs1==x2, rs2==x4, rd==x3, 
// opcode: clmulr ; op1:x2; op2:x4; dest:x3; op1val:0xffffffff;  op2val:0xffffffef
TEST_RR_OP(clmulr, x3, x2, x4, 0x00000000, 0xffffffff, 0xffffffef, x8, 12, x9)

inst_29:
// rs1==x4, rs2==x3, rd==x2, 
// opcode: clmulr ; op1:x4; op2:x3; dest:x2; op1val:0xffffffff;  op2val:0xfffffff7
TEST_RR_OP(clmulr, x2, x4, x3, 0x00000000, 0xffffffff, 0xfffffff7, x8, 16, x9)

inst_30:
// rs1==x1, 
// opcode: clmulr ; op1:x1; op2:x30; dest:x31; op1val:0xffffffff;  op2val:0xfffffffb
TEST_RR_OP(clmulr, x31, x1, x30, 0x00000000, 0xffffffff, 0xfffffffb, x8, 20, x9)

inst_31:
// rs1==x0, 
// opcode: clmulr ; op1:x0; op2:x30; dest:x31; op1val:0x0;  op2val:0xfffffffd
TEST_RR_OP(clmulr, x31, x0, x30, 0x00000000, 0x0, 0xfffffffd, x8, 24, x9)

inst_32:
// rs2==x1, 
// opcode: clmulr ; op1:x30; op2:x1; dest:x31; op1val:0xffffffff;  op2val:0xfffffffe
TEST_RR_OP(clmulr, x31, x30, x1, 0x00000000, 0xffffffff, 0xfffffffe, x8, 28, x9)

inst_33:
// rs2==x0, 
// opcode: clmulr ; op1:x30; op2:x0; dest:x31; op1val:0x7fffffff;  op2val:0x0
TEST_RR_OP(clmulr, x31, x30, x0, 0x00000000, 0x7fffffff, 0x0, x8, 32, x9)

inst_34:
// rd==x1, 
// opcode: clmulr ; op1:x31; op2:x30; dest:x1; op1val:0xbfffffff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x1, x31, x30, 0x00000000, 0xbfffffff, 0xffffffff, x8, 36, x9)

inst_35:
// rd==x0, 
// opcode: clmulr ; op1:x31; op2:x30; dest:x0; op1val:0xdfffffff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x0, x31, x30, 0x00000000, 0xdfffffff, 0xffffffff, x8, 40, x9)

inst_36:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xefffffff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xefffffff, 0xffffffff, x8, 44, x9)

inst_37:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xf7ffffff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xf7ffffff, 0xffffffff, x8, 48, x9)

inst_38:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xfbffffff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xfbffffff, 0xffffffff, x8, 52, x9)

inst_39:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xfdffffff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xfdffffff, 0xffffffff, x8, 56, x9)

inst_40:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xfeffffff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xfeffffff, 0xffffffff, x8, 60, x9)

inst_41:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xff7fffff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xff7fffff, 0xffffffff, x8, 64, x9)

inst_42:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffbfffff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffbfffff, 0xffffffff, x8, 68, x9)

inst_43:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffdfffff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffdfffff, 0xffffffff, x8, 72, x9)

inst_44:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffefffff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffefffff, 0xffffffff, x8, 76, x9)

inst_45:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xfff7ffff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xfff7ffff, 0xffffffff, x8, 80, x9)

inst_46:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xfffbffff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xfffbffff, 0xffffffff, x8, 84, x9)

inst_47:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xfffdffff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xfffdffff, 0xffffffff, x8, 88, x9)

inst_48:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xfffeffff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xfffeffff, 0xffffffff, x8, 92, x9)

inst_49:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffff7fff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffff7fff, 0xffffffff, x8, 96, x9)

inst_50:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffbfff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffbfff, 0xffffffff, x8, 100, x9)

inst_51:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffdfff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffdfff, 0xffffffff, x8, 104, x9)

inst_52:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffefff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffefff, 0xffffffff, x8, 108, x9)

inst_53:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xfffff7ff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xfffff7ff, 0xffffffff, x8, 112, x9)

inst_54:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xfffffbff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xfffffbff, 0xffffffff, x8, 116, x9)

inst_55:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xfffffdff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xfffffdff, 0xffffffff, x8, 120, x9)

inst_56:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xfffffeff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xfffffeff, 0xffffffff, x8, 124, x9)

inst_57:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffff7f;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffff7f, 0xffffffff, x8, 128, x9)

inst_58:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffbf;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffbf, 0xffffffff, x8, 132, x9)

inst_59:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffdf;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffdf, 0xffffffff, x8, 136, x9)

inst_60:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffef;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffef, 0xffffffff, x8, 140, x9)

inst_61:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xfffffff7;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xfffffff7, 0xffffffff, x8, 144, x9)

inst_62:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffb;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xfffffffb, 0xffffffff, x8, 148, x9)

inst_63:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffd;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xfffffffd, 0xffffffff, x8, 152, x9)

inst_64:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xfffffffe;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xfffffffe, 0xffffffff, x8, 156, x9)

inst_65:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x80000000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x80000000, x8, 160, x9)

inst_66:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x40000000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x40000000, x8, 164, x9)

inst_67:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x20000000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x20000000, x8, 168, x9)

inst_68:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x10000000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x10000000, x8, 172, x9)

inst_69:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x8000000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x8000000, x8, 176, x9)

inst_70:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x4000000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x4000000, x8, 180, x9)

inst_71:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x2000000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x2000000, x8, 184, x9)

inst_72:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x1000000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x1000000, x8, 188, x9)

inst_73:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x800000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x800000, x8, 192, x9)

inst_74:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x400000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x400000, x8, 196, x9)

inst_75:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x200000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x200000, x8, 200, x9)

inst_76:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x100000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x100000, x8, 204, x9)

inst_77:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x80000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x80000, x8, 208, x9)

inst_78:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x40000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x40000, x8, 212, x9)

inst_79:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x20000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x20000, x8, 216, x9)

inst_80:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x10000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x10000, x8, 220, x9)

inst_81:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x8000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x8000, x8, 224, x9)

inst_82:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x4000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x4000, x8, 228, x9)

inst_83:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x2000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x2000, x8, 232, x9)

inst_84:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x1000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x1000, x8, 236, x9)

inst_85:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x800
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x800, x8, 240, x9)

inst_86:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x400
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x400, x8, 244, x9)

inst_87:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x200
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x200, x8, 248, x9)

inst_88:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x100
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x100, x8, 252, x9)

inst_89:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x80
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x80, x8, 256, x9)

inst_90:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x40
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x40, x8, 260, x9)

inst_91:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x20
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x20, x8, 264, x9)

inst_92:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x10
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x10, x8, 268, x9)

inst_93:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x8
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x8, x8, 272, x9)

inst_94:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x4
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x4, x8, 276, x9)

inst_95:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x1;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x1, 0xffffffff, x8, 280, x9)

inst_96:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x91766f62;  op2val:0x5570084b
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x91766f62, 0x5570084b, x8, 284, x9)

inst_97:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xc0fe15dd;  op2val:0x9f053821
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xc0fe15dd, 0x9f053821, x8, 288, x9)

inst_98:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xdc80d916;  op2val:0x2a2a146d
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xdc80d916, 0x2a2a146d, x8, 292, x9)

inst_99:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x952acffe;  op2val:0x25ae27ee
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x952acffe, 0x25ae27ee, x8, 296, x9)

inst_100:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x40a5ff52;  op2val:0xb6f9706f
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x40a5ff52, 0xb6f9706f, x8, 300, x9)

inst_101:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xe3f4fca3;  op2val:0xa6c9253a
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xe3f4fca3, 0xa6c9253a, x8, 304, x9)

inst_102:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xc2f1c53e;  op2val:0xd05668ae
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xc2f1c53e, 0xd05668ae, x8, 308, x9)

inst_103:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x9722c9a6;  op2val:0x7bcad7c4
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x9722c9a6, 0x7bcad7c4, x8, 312, x9)

inst_104:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xf7f1305a;  op2val:0x9bedfe39
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xf7f1305a, 0x9bedfe39, x8, 316, x9)

inst_105:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xd75739f8;  op2val:0xe6fff3d9
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xd75739f8, 0xe6fff3d9, x8, 320, x9)

inst_106:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x90efb625;  op2val:0x3150e5fa
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x90efb625, 0x3150e5fa, x8, 324, x9)

inst_107:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x1fc493ca;  op2val:0x65408c73
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x1fc493ca, 0x65408c73, x8, 328, x9)

inst_108:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x8e2eac2a;  op2val:0xd169a3f8
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x8e2eac2a, 0xd169a3f8, x8, 332, x9)

inst_109:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x35f9377f;  op2val:0xf4c30307
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x35f9377f, 0xf4c30307, x8, 336, x9)

inst_110:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x58d548aa;  op2val:0xa0569d76
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x58d548aa, 0xa0569d76, x8, 340, x9)

inst_111:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x55d98c6e;  op2val:0x2daf9ac7
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x55d98c6e, 0x2daf9ac7, x8, 344, x9)

inst_112:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x74b8de87;  op2val:0xf273b44c
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x74b8de87, 0xf273b44c, x8, 348, x9)

inst_113:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xccce240c;  op2val:0x886c3a30
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xccce240c, 0x886c3a30, x8, 352, x9)

inst_114:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xb49c83dc;  op2val:0xbb61a9cd
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xb49c83dc, 0xbb61a9cd, x8, 356, x9)

inst_115:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x254a9493;  op2val:0xc5521660
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x254a9493, 0xc5521660, x8, 360, x9)

inst_116:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0xaaaaaaaa
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0xaaaaaaaa, x8, 364, x9)

inst_117:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x55555555
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x55555555, x8, 368, x9)

inst_118:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xaaaaaaaa;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xaaaaaaaa, 0xffffffff, x8, 372, x9)

inst_119:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x55555555;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x55555555, 0xffffffff, x8, 376, x9)

inst_120:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x0;  op2val:0x1000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x0, 0x1000, x8, 380, x9)

inst_121:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x0;  op2val:0x1
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x0, 0x1, x8, 384, x9)

inst_122:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x1;  op2val:0x0
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x1, 0x0, x8, 388, x9)

inst_123:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x1;  op2val:0x1000
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x1, 0x1000, x8, 392, x9)

inst_124:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x1;  op2val:0x1
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x1, 0x1, x8, 396, x9)

inst_125:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0x2
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0x2, x8, 400, x9)

inst_126:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x80000000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x80000000, 0xffffffff, x8, 404, x9)

inst_127:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x40000000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x40000000, 0xffffffff, x8, 408, x9)

inst_128:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x20000000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x20000000, 0xffffffff, x8, 412, x9)

inst_129:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x10000000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x10000000, 0xffffffff, x8, 416, x9)

inst_130:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x8000000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x8000000, 0xffffffff, x8, 420, x9)

inst_131:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x4000000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x4000000, 0xffffffff, x8, 424, x9)

inst_132:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x2000000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x2000000, 0xffffffff, x8, 428, x9)

inst_133:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x1000000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x1000000, 0xffffffff, x8, 432, x9)

inst_134:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x800000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x800000, 0xffffffff, x8, 436, x9)

inst_135:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x400000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x400000, 0xffffffff, x8, 440, x9)

inst_136:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x200000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x200000, 0xffffffff, x8, 444, x9)

inst_137:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x100000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x100000, 0xffffffff, x8, 448, x9)

inst_138:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x80000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x80000, 0xffffffff, x8, 452, x9)

inst_139:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x40000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x40000, 0xffffffff, x8, 456, x9)

inst_140:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x20000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x20000, 0xffffffff, x8, 460, x9)

inst_141:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x10000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x10000, 0xffffffff, x8, 464, x9)

inst_142:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x8000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x8000, 0xffffffff, x8, 468, x9)

inst_143:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x4000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x4000, 0xffffffff, x8, 472, x9)

inst_144:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x2000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x2000, 0xffffffff, x8, 476, x9)

inst_145:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x1000;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x1000, 0xffffffff, x8, 480, x9)

inst_146:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x800;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x800, 0xffffffff, x8, 484, x9)

inst_147:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x400;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x400, 0xffffffff, x8, 488, x9)

inst_148:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x200;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x200, 0xffffffff, x8, 492, x9)

inst_149:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x100;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x100, 0xffffffff, x8, 496, x9)

inst_150:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x80;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x80, 0xffffffff, x8, 500, x9)

inst_151:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x40;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x40, 0xffffffff, x8, 504, x9)

inst_152:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x20;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x20, 0xffffffff, x8, 508, x9)

inst_153:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x10;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x10, 0xffffffff, x8, 512, x9)

inst_154:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x8;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x8, 0xffffffff, x8, 516, x9)

inst_155:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x4;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x4, 0xffffffff, x8, 520, x9)

inst_156:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x2;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x2, 0xffffffff, x8, 524, x9)

inst_157:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x0;  op2val:0x0
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x0, 0x0, x8, 528, x9)

inst_158:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0xdfffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0xdfffffff, x8, 532, x9)

inst_159:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xffffffff;  op2val:0xfffffffd
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xffffffff, 0xfffffffd, x8, 536, x9)

inst_160:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0x7fffffff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0x7fffffff, 0xffffffff, x8, 540, x9)

inst_161:
// 
// opcode: clmulr ; op1:x30; op2:x29; dest:x31; op1val:0xdfffffff;  op2val:0xffffffff
TEST_RR_OP(clmulr, x31, x30, x29, 0x00000000, 0xdfffffff, 0xffffffff, x8, 544, x9)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x1_1:
    .fill 25*(XLEN/32),4,0xdeadbeef


signature_x8_0:
    .fill 137*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
