
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version   : 0.4.1
// timestamp : Tue Dec 15 15:36:11 2020 GMT
// usage     : riscv_ctg \
//                  -- cgf ('/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/dataset.cgf', '/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/rv32i.cgf') \
//                  -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the jalr instruction of the RISC-V I extension for the jalr covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")

.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",jalr)

RVTEST_SIGBASE( x10,signature_x10_1)

inst_0:
// rs1 != rd, rs1==x4, rd==x25, imm_val > 0, imm_val == 64
// opcode: jalr; op1:x4; dest:x25; immval:0x40; align:0 
TEST_JALR_OP(x15, x25, x4, 0x40, x10, 0,0)

inst_1:
// rs1 == rd, rs1==x17, rd==x17, imm_val < 0, imm_val == -257
// opcode: jalr; op1:x17; dest:x17; immval:-0x101; align:0 
TEST_JALR_OP(x15, x17, x17, -0x101, x10, 4,0)

inst_2:
// rs1==x3, rd==x16, imm_val == 1, 
// opcode: jalr; op1:x3; dest:x16; immval:0x1; align:0 
TEST_JALR_OP(x15, x16, x3, 0x1, x10, 8,0)

inst_3:
// rs1==x23, rd==x12, imm_val == 2, 
// opcode: jalr; op1:x23; dest:x12; immval:0x2; align:0 
TEST_JALR_OP(x15, x12, x23, 0x2, x10, 12,0)

inst_4:
// rs1==x27, rd==x13, imm_val == 4, 
// opcode: jalr; op1:x27; dest:x13; immval:0x4; align:0 
TEST_JALR_OP(x15, x13, x27, 0x4, x10, 16,0)

inst_5:
// rs1==x6, rd==x8, imm_val == 8, 
// opcode: jalr; op1:x6; dest:x8; immval:0x8; align:0 
TEST_JALR_OP(x15, x8, x6, 0x8, x10, 20,0)

inst_6:
// rs1==x12, rd==x30, imm_val == 16, 
// opcode: jalr; op1:x12; dest:x30; immval:0x10; align:0 
TEST_JALR_OP(x15, x30, x12, 0x10, x10, 24,0)

inst_7:
// rs1==x31, rd==x0, imm_val == 32, 
// opcode: jalr; op1:x31; dest:x0; immval:0x20; align:0 
TEST_JALR_OP(x15, x0, x31, 0x20, x10, 28,0)

inst_8:
// rs1==x20, rd==x3, imm_val == 128, 
// opcode: jalr; op1:x20; dest:x3; immval:0x80; align:0 
TEST_JALR_OP(x15, x3, x20, 0x80, x10, 32,0)

inst_9:
// rs1==x13, rd==x19, imm_val == 256, 
// opcode: jalr; op1:x13; dest:x19; immval:0x100; align:0 
TEST_JALR_OP(x15, x19, x13, 0x100, x10, 36,0)

inst_10:
// rs1==x8, rd==x29, imm_val == 512, 
// opcode: jalr; op1:x8; dest:x29; immval:0x200; align:0 
TEST_JALR_OP(x15, x29, x8, 0x200, x10, 40,0)

inst_11:
// rs1==x30, rd==x22, imm_val == 1024, 
// opcode: jalr; op1:x30; dest:x22; immval:0x400; align:0 
TEST_JALR_OP(x15, x22, x30, 0x400, x10, 44,0)

inst_12:
// rs1==x29, rd==x21, imm_val == -2048, 
// opcode: jalr; op1:x29; dest:x21; immval:-0x800; align:0 
TEST_JALR_OP(x15, x21, x29, -0x800, x10, 48,0)

inst_13:
// rs1==x18, rd==x11, imm_val == -2, 
// opcode: jalr; op1:x18; dest:x11; immval:-0x2; align:0 
TEST_JALR_OP(x15, x11, x18, -0x2, x10, 52,0)

inst_14:
// rs1==x21, rd==x28, imm_val == -3, 
// opcode: jalr; op1:x21; dest:x28; immval:-0x3; align:0 
TEST_JALR_OP(x15, x28, x21, -0x3, x10, 56,0)

inst_15:
// rs1==x24, rd==x14, imm_val == -5, 
// opcode: jalr; op1:x24; dest:x14; immval:-0x5; align:0 
TEST_JALR_OP(x15, x14, x24, -0x5, x10, 60,0)

inst_16:
// rs1==x2, rd==x6, imm_val == -9, 
// opcode: jalr; op1:x2; dest:x6; immval:-0x9; align:0 
TEST_JALR_OP(x15, x6, x2, -0x9, x10, 64,0)

inst_17:
// rs1==x1, rd==x5, imm_val == -17, 
// opcode: jalr; op1:x1; dest:x5; immval:-0x11; align:0 
TEST_JALR_OP(x15, x5, x1, -0x11, x10, 68,0)

inst_18:
// rs1==x5, rd==x18, imm_val == -33, 
// opcode: jalr; op1:x5; dest:x18; immval:-0x21; align:0 
TEST_JALR_OP(x15, x18, x5, -0x21, x10, 72,0)

inst_19:
// rs1==x9, rd==x7, imm_val == -65, 
// opcode: jalr; op1:x9; dest:x7; immval:-0x41; align:0 
TEST_JALR_OP(x15, x7, x9, -0x41, x10, 76,0)
RVTEST_SIGBASE( x3,signature_x3_0)

inst_20:
// rs1==x25, rd==x10, imm_val == -129, 
// opcode: jalr; op1:x25; dest:x10; immval:-0x81; align:0 
TEST_JALR_OP(x5, x10, x25, -0x81, x3, 0,0)

inst_21:
// rs1==x11, rd==x15, imm_val == -513, 
// opcode: jalr; op1:x11; dest:x15; immval:-0x201; align:0 
TEST_JALR_OP(x5, x15, x11, -0x201, x3, 4,0)

inst_22:
// rs1==x19, rd==x9, imm_val == -1025, 
// opcode: jalr; op1:x19; dest:x9; immval:-0x401; align:0 
TEST_JALR_OP(x5, x9, x19, -0x401, x3, 8,0)

inst_23:
// rs1==x7, rd==x20, imm_val == 2047, 
// opcode: jalr; op1:x7; dest:x20; immval:0x7ff; align:0 
TEST_JALR_OP(x5, x20, x7, 0x7ff, x3, 12,0)

inst_24:
// rs1==x14, rd==x26, imm_val == 1365, 
// opcode: jalr; op1:x14; dest:x26; immval:0x555; align:0 
TEST_JALR_OP(x5, x26, x14, 0x555, x3, 16,0)

inst_25:
// rs1==x15, rd==x4, imm_val == -1366, 
// opcode: jalr; op1:x15; dest:x4; immval:-0x556; align:0 
TEST_JALR_OP(x5, x4, x15, -0x556, x3, 20,0)

inst_26:
// rs1==x22, rd==x24, 
// opcode: jalr; op1:x22; dest:x24; immval:-0x800; align:0 
TEST_JALR_OP(x5, x24, x22, -0x800, x3, 24,0)

inst_27:
// rs1==x26, rd==x23, 
// opcode: jalr; op1:x26; dest:x23; immval:-0x800; align:0 
TEST_JALR_OP(x5, x23, x26, -0x800, x3, 28,0)

inst_28:
// rs1==x28, rd==x2, 
// opcode: jalr; op1:x28; dest:x2; immval:-0x800; align:0 
TEST_JALR_OP(x5, x2, x28, -0x800, x3, 32,0)

inst_29:
// rs1==x10, rd==x1, 
// opcode: jalr; op1:x10; dest:x1; immval:-0x800; align:0 
TEST_JALR_OP(x5, x1, x10, -0x800, x3, 36,0)

inst_30:
// rs1==x16, rd==x31, 
// opcode: jalr; op1:x16; dest:x31; immval:-0x800; align:0 
TEST_JALR_OP(x5, x31, x16, -0x800, x3, 40,0)

inst_31:
// rd==x27, 
// opcode: jalr; op1:x16; dest:x27; immval:-0x800; align:0 
TEST_JALR_OP(x5, x27, x16, -0x800, x3, 44,0)

inst_32:
// imm_val == 32, 
// opcode: jalr; op1:x10; dest:x11; immval:0x20; align:0 
TEST_JALR_OP(x5, x11, x10, 0x20, x3, 48,0)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4

rvtest_data:
.word 0xbabecafe
.word 0xbabecafe
.word 0xbabecafe
.word 0xbabecafe
RVTEST_DATA_END


RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x10_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x10_1:
    .fill 20*(XLEN/32),4,0xdeadbeef


signature_x3_0:
    .fill 13*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
