# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore

datasets: 
  rv32e_regs_mx0: &rv32e_regs_mx0
    x1: 0
    x2: 0
    x3: 0
    x4: 0
    x5: 0
    x6: 0
    x7: 0
    x8: 0
    x9: 0
    x10: 0
    x11: 0
    x12: 0
    x13: 0
    x14: 0
    x15: 0
  rv32e_regs: &rv32e_regs
    x0: 0
    x1: 0
    x2: 0
    x3: 0
    x4: 0
    x5: 0
    x6: 0
    x7: 0
    x8: 0
    x9: 0
    x10: 0
    x11: 0
    x12: 0
    x13: 0
    x14: 0
    x15: 0

  all_regs: &all_regs
    x0: 0
    x1: 0
    x2: 0
    x3: 0
    x4: 0
    x5: 0
    x6: 0
    x7: 0
    x8: 0
    x9: 0
    x10: 0
    x11: 0
    x12: 0
    x13: 0
    x14: 0
    x15: 0
    x16: 0
    x17: 0
    x18: 0
    x19: 0
    x20: 0
    x21: 0
    x22: 0
    x23: 0
    x24: 0
    x25: 0
    x26: 0
    x27: 0
    x28: 0
    x29: 0
    x30: 0
    x31: 0

  c_regs: &c_regs
    x8: 0
    x9: 0
    x10: 0
    x11: 0
    x12: 0
    x13: 0
    x14: 0
    x15: 0
  
  all_regs_mx2: &all_regs_mx2
    x1: 0
    x3: 0
    x4: 0
    x5: 0
    x6: 0
    x7: 0
    x8: 0
    x9: 0
    x10: 0
    x11: 0
    x12: 0
    x13: 0
    x14: 0
    x15: 0
    x16: 0
    x17: 0
    x18: 0
    x19: 0
    x20: 0
    x21: 0
    x22: 0
    x23: 0
    x24: 0
    x25: 0
    x26: 0
    x27: 0
    x28: 0
    x29: 0
    x30: 0
    x31: 0

  all_regs_mx0: &all_regs_mx0
    x1: 0
    x2: 0
    x3: 0
    x4: 0
    x5: 0
    x6: 0
    x7: 0
    x8: 0
    x9: 0
    x10: 0
    x11: 0
    x12: 0
    x13: 0
    x14: 0
    x15: 0
    x16: 0
    x17: 0
    x18: 0
    x19: 0
    x20: 0
    x21: 0
    x22: 0
    x23: 0
    x24: 0
    x25: 0
    x26: 0
    x27: 0
    x28: 0
    x29: 0
    x30: 0
    x31: 0

  cbfmt_immval_sgn: &cbfmt_immval_sgn
    'imm_val == (-2**(6-1))': 0
    'imm_val == 0': 0
    'imm_val == (2**(6-1)-1)': 0
    'imm_val == 1': 0

  rfmt_op_comb: &rfmt_op_comb
    'rs1 == rs2 != rd': 0
    'rs1 == rd != rs2': 0
    'rs2 == rd != rs1': 0
    'rs1 == rs2 == rd': 0
    'rs1 != rs2  and rs1 != rd and rs2 != rd': 0

  ifmt_op_comb: &ifmt_op_comb
    'rs1 == rd': 0
    'rs1 != rd': 0

  sfmt_op_comb: &sfmt_op_comb
    'rs1 == rs2': 0
    'rs1 != rs2': 0
  
  base_rs1val_sgn: &base_rs1val_sgn
    'rs1_val == (-2**(xlen-1))': 0
    'rs1_val == 0': 0
    'rs1_val == (2**(xlen-1)-1)': 0
    'rs1_val == 1': 0
  
  base_rs2val_sgn: &base_rs2val_sgn
    'rs2_val == (-2**(xlen-1))': 0
    'rs2_val == 0': 0
    'rs2_val == (2**(xlen-1)-1)': 0
    'rs2_val == 1': 0
  
  base_rs1val_unsgn: &base_rs1val_unsgn
    'rs1_val == 0': 0
    'rs1_val == (2**(xlen)-1)': 0
    'rs1_val == 1': 0
  
  base_rs2val_unsgn: &base_rs2val_unsgn
    'rs2_val == 0': 0
    'rs2_val == (2**(xlen)-1)': 0
    'rs2_val == 1': 0

  rfmt_val_comb_sgn: &rfmt_val_comb_sgn
    'rs1_val > 0 and rs2_val > 0': 0
    'rs1_val > 0 and rs2_val < 0': 0
    'rs1_val < 0 and rs2_val < 0': 0
    'rs1_val < 0 and rs2_val > 0': 0
    'rs1_val == rs2_val': 0
    'rs1_val != rs2_val': 0
  
  rfmt_val_comb_unsgn: &rfmt_val_comb_unsgn
    'rs1_val > 0 and rs2_val > 0': 0
    'rs1_val == rs2_val and rs1_val > 0 and rs2_val > 0': 0
    'rs1_val != rs2_val and rs1_val > 0 and rs2_val > 0': 0

  ifmt_val_comb_sgn: &ifmt_val_comb_sgn
    'rs1_val == imm_val': 0
    'rs1_val != imm_val': 0
    'rs1_val > 0 and imm_val > 0': 0
    'rs1_val > 0 and imm_val < 0': 0
    'rs1_val < 0 and imm_val > 0': 0
    'rs1_val < 0 and imm_val < 0': 0
  
  ifmt_val_comb_unsgn: &ifmt_val_comb_unsgn
    'rs1_val == imm_val and rs1_val > 0 and imm_val > 0': 0
    'rs1_val != imm_val and rs1_val > 0 and imm_val > 0': 0

  ifmt_base_immval_sgn: &ifmt_base_immval_sgn
    'imm_val == (-2**(12-1))': 0
    'imm_val == 0': 0
    'imm_val == (2**(12-1)-1)': 0
    'imm_val == 1': 0
  
  ifmt_base_immval_unsgn: &ifmt_base_immval_unsgn
    'imm_val == 0': 0
    'imm_val == (2**(12)-1)': 0
    'imm_val == 1': 0

  ifmt_base_shift: &ifmt_base_shift
    'rs1_val < 0 and imm_val > 0 and imm_val < xlen': 0
    'rs1_val > 0 and imm_val > 0 and imm_val < xlen': 0
    'rs1_val < 0 and imm_val == 0': 0
    'rs1_val > 0 and imm_val == 0': 0
    'rs1_val < 0 and imm_val == (xlen-1)': 0
    'rs1_val > 0 and imm_val == (xlen-1)': 0
    'rs1_val == imm_val and imm_val > 0 and imm_val < xlen': 0
    'rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < xlen': 0
    'rs1_val == 0 and imm_val >= 0 and imm_val < xlen': 0
    'rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < xlen': 0
    'rs1_val == 1 and imm_val >= 0 and imm_val < xlen': 0

  ifmt_base_shift_32w: &ifmt_base_shift_32w
    'rs1_val < 0 and imm_val > 0 and imm_val < 32': 0
    'rs1_val > 0 and imm_val > 0 and imm_val < 32': 0
    'rs1_val < 0 and imm_val == 0': 0
    'rs1_val > 0 and imm_val == 0': 0
    'rs1_val < 0 and imm_val == 31': 0
    'rs1_val > 0 and imm_val == 31': 0
    'rs1_val == imm_val and imm_val > 0 and imm_val < 32': 0
    'rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < 32': 0
    'rs1_val == 0 and imm_val >= 0 and imm_val < 32': 0
    'rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < 32': 0
    'rs1_val == 1 and imm_val >= 0 and imm_val < 32': 0


  rfmt_base_shift: &rfmt_base_shift
    'rs1_val < 0 and rs2_val > 0 and rs2_val < xlen': 0
    'rs1_val > 0 and rs2_val > 0 and rs2_val < xlen': 0
    'rs1_val < 0 and rs2_val == 0': 0
    'rs1_val > 0 and rs2_val == 0': 0
    'rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen': 0
    'rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen': 0
    'rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen': 0
    'rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen': 0
    'rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen': 0

  bfmt_base_branch_val_align_sgn: &bfmt_base_branch_val_align_sgn
    'rs1_val > 0 and rs2_val > 0 and imm_val & 0x03 == 0': 0
    'rs1_val > 0 and rs2_val < 0 and imm_val & 0x03 == 0': 0
    'rs1_val < 0 and rs2_val < 0 and imm_val & 0x03 == 0': 0
    'rs1_val < 0 and rs2_val > 0 and imm_val & 0x03 == 0': 0
    'rs1_val == rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0
    'rs1_val == rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0
    'rs1_val > rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0
    'rs1_val > rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0
    'rs1_val < rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0
    'rs1_val < rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0
  
  bfmt_base_branch_val_align_unsgn: &bfmt_base_branch_val_align_unsgn
    'rs1_val > 0 and rs2_val > 0': 0
    'rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val > 0': 0
    'rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val < 0': 0
    'rs1_val > 0 and rs2_val > 0 and rs1_val > rs2_val and imm_val > 0 ': 0
    'rs1_val > 0 and rs2_val > 0 and rs1_val > rs2_val and imm_val < 0 ': 0
    'rs1_val > 0 and rs2_val > 0 and rs1_val < rs2_val and imm_val > 0 ': 0
    'rs1_val > 0 and rs2_val > 0 and rs1_val < rs2_val and imm_val < 0 ': 0

  rs1val_walking: &rs1val_walking
    'walking_ones("rs1_val", xlen)': 0
    'walking_zeros("rs1_val", xlen)': 0
    'alternate("rs1_val",xlen)': 0

  rs2val_walking: &rs2val_walking
    'walking_ones("rs2_val", xlen)': 0
    'walking_zeros("rs2_val", xlen)': 0
    'alternate("rs2_val",xlen)': 0
  
  ifmt_immval_walking: &ifmt_immval_walking
    'walking_ones("imm_val", 12)': 0
    'walking_zeros("imm_val", 12)': 0
    'alternate("imm_val",12)': 0
  
  rs1val_walking_unsgn: &rs1val_walking_unsgn
    'walking_ones("rs1_val", xlen,False)': 0
    'walking_zeros("rs1_val", xlen,False)': 0
    'alternate("rs1_val",xlen,False)': 0
  
  rs2val_walking_unsgn: &rs2val_walking_unsgn
    'walking_ones("rs2_val", xlen,False)': 0
    'walking_zeros("rs2_val", xlen,False)': 0
    'alternate("rs2_val",xlen,False)': 0

  crfmt_val_comb_sgn: &crfmt_val_comb_sgn
    'rs2_val > 0': 0
    'rs2_val < 0': 0

  cbimm_val_walking: &cbimm_val_walking
    'walking_ones("imm_val", 6)': 0
    'walking_zeros("imm_val", 6)': 0
    'alternate("imm_val",6)': 0
  
  ifmt_immval_walking_unsgn: &ifmt_immval_walking_unsgn
    'walking_ones("imm_val", 12,False)': 0
    'walking_zeros("imm_val", 12,False)': 0
    'alternate("imm_val",12,False)': 0

