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# Mixed-precision Neural Networks on RISC-V Cores
- [Overview](#Overview)
- [Build the RISC-V Toolchain](#Build-the-RISC-V-Toolchain)
- [Mixed Precision Quantization](#Mixed-Precision-Quantization)
- [RISC-V Architecture](#RISC-V-Architecture)
- [Inference Simulation Using Verilator](#Inference-Simulation-Using-Verilator)
## Overview
The growing interest in deploying machine learning (ML) applications on devices with restricted processing power and energy capacity underscores the necessity for computing solutions that not only excel in power and memory efficiency but also ensure low latency for time-sensitive applications. Research has shown that individual parameters with varying low precision, can attain accuracies comparable to full-precision counterparts. However, modern embedded microprocessors provide very limited support for mixed-precision Neural Networks regarding both Instruction Set Architecture (ISA) extensions and their hardware design for efficient execution of mixed-precision operations, i.e. introducing several performance bottlenecks due to numerous instructions for data packing and unpacking, arithmetic unit under-utilizations etc.
In this work, we propose ISA extensions tailored to mixed precision hardware optimizations, targeting energy-efficient Deep Neural Network inference on leading RISC-V CPU architectures. To this end, we introduce a hardware-software co-design framework that enables cooperative hardware design, mixed-precision quantization, ISA extensions and inference in cycle-accurate emulations.
This repository includes:
1. Instructions for updating the RISC-V toolchain with new custom instructions.
2. Examples demonstrating the quantization of neural networks using mixed-precision variables. Techniques such as Post-Training Quantization (PTQ) and Quantization-Aware Training (QAT) are employed, leveraging the Brevitas library.
3. Details on the RISC-V architecture, which extends the lowRISC Ibex core (written in SystemVerilog).
4. Inference codes written in C, both with and without the integration of new instructions. These codes were simulated on the RISC-V processor with the use of Verilator. The repository provides comprehensive instructions for building the simulations and testing the results.
<!-- - Instructions on mapping the processor onto an FPGA board or an ASIC design using tools like Vivado and Synopsys, along with procedures for retrieving data regarding area, timing, and power consumption.
-->
A brief overview of the whole process can be seen in the following flowchart:
<p align="center">
<img width="55%" alt="workflow" src="https://github.com/alexmr09/ISA-extensions-for-Multi-Pumped-Soft-SIMD-Operations/blob/main/assets/figures/workflow_page-0001.jpg">
</p>
## Build the RISC-V Toolchain
To get started, we'll first build the RISC-V toolchain. Before proceeding, ensure that all necessary dependencies are installed on the system:
```
sudo apt-get install autoconf automake autotools-dev curl python3 libmpc-dev libmpfr-dev libgmp-dev gawk \
build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev
```
Next, clone the toolchain from the official repository:
```
git clone https://github.com/riscv/riscv-gnu-toolchain
cd riscv-gnu-toolchain
git submodule update --init --recursive
```
To implement the modifications in the RISC-V GNU toolchain, adhere to the changes outlined for the following files:
1. **File Path**: `path/to/riscv-gnu-toolchain/riscv-binutils-gdb/include/opcode/riscv-opc.h`
```c
#ifndef RISCV_ENCODING_H
#define RISCV_ENCODING_H
#define MATCH_NEUR_INIT 0x1047
#define MASK_NEUR_INIT 0xfe00707f
#define MATCH_NEUR_MACC_8B 0x10002047
#define MASK_NEUR_MACC_8B 0xfe00707f
#define MATCH_NEUR_MACC_4B 0x08002047
#define MASK_NEUR_MACC_4B 0xfe00707f
#define MATCH_NEUR_MACC_2B 0x04002047
#define MASK_NEUR_MACC_2B 0xfe00707f
#define MATCH_NEUR_RES 0x4047
#define MASK_NEUR_RES 0xfe00707f
...
#endif /* RISCV_ENCODING_H */
#ifdef DECLARE_INSN
DECLARE_INSN(neur_init, MATCH_NEUR_INIT, MASK_NEUR_INIT)
DECLARE_INSN(nn_mac_8b, MATCH_NEUR_MACC_8B, MASK_NEUR_MACC_8B
DECLARE_INSN(nn_mac_4b, MATCH_NEUR_MACC_4B, MASK_NEUR_MACC_4B)
DECLARE_INSN(nn_mac_2b, MATCH_NEUR_MACC_2B, MASK_NEUR_MACC_2B)
DECLARE_INSN(neur_res, MATCH_NEUR_RES, MASK_NEUR_RES)
#endif /* DECLARE_INSN */
```
2. **File Path**: `path/to/riscv-gnu-toolchain/riscv-binutils-gdb/opcodes/riscv-opc.c`
```c
...
const struct riscv_opcode riscv_opcodes[] =
{
{"neur_init", 0, INSN_CLASS_I, "d,s,t", MATCH_NEUR_INIT, MASK_NEUR_INIT, match_opcode, 0},
{"nn_mac_8b", 0, INSN_CLASS_I, "d,s,t", MATCH_NEUR_MACC_8B, MASK_NEUR_MACC_8B, match_opcode, 0},
{"nn_mac_4b", 0, INSN_CLASS_I, "d,s,t", MATCH_NEUR_MACC_4B, MASK_NEUR_MACC_4B, match_opcode, 0},
{"nn_mac_2b", 0, INSN_CLASS_I, "d,s,t", MATCH_NEUR_MACC_2B, MASK_NEUR_MACC_2B, match_opcode, 0},
{"neur_res", 0, INSN_CLASS_I, "d,s,t", MATCH_NEUR_RES, MASK_NEUR_RES, match_opcode, 0},
...
```
Now, let's configure and install the toolchain, with the custom instructions included. For the Ibex core, we require the RV32IMC instruction set:
```
./configure --prefix=/opt/riscv --with-arch=rv32imc --with-abi=ilp32 --with-isa-spec=2.2
sudo make && make install
sudo make clean
```
We will need to make sure that the directories containing the RISC-V tools are included in the **PATH** environment variable. Since our binaries are located in **'/opt/riscv/bin'** , we must add it to our PATH in the shell configuration file (**'~/.bashrc'** or **'~/.bash_profile'**):
```
export PATH=$PATH:/opt/riscv/bin
```
After adding this line, apply the changes:
```
source ~/.bashrc
```
Finally, we should verify that the RISC-V GCC compiler and other tools are accessible. Run the following command to check the RISC-V GCC compiler version:
```
riscv32-unknown-elf-gcc --version
```
You should see output similar to:
```
riscv32-unknown-elf-gcc (gc891d8dc23e) 13.2.0
Copyright (C) 2023 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
```
## Mixed Precision Quantization
The next step involves creating the Quantized Model using the [Brevitas](https://github.com/Xilinx/brevitas) Library. To begin, we must acquire the full-precision model, either by importing a pre-trained version or training it from scratch. Once we have the model, we will evaluate its accuracy on the given dataset. Following this, we will replicate the model's architecture and substitute its layers with the corresponding quantized versions available in the Brevitas library. Finally, we need to determine the appropriate weight precision for each layer. Two options can be explored:
1. "**Exhaustive**" Design Space Exploration. This method allows us to observe how our network behaves when utilizing different weight configurations. It's suitable for relatively small models (up to 5 or 6 layers) and ensures finding the optimal solution. However, for larger models, efficiency becomes crucial. To expedite the process, we can either uniformly quantize consecutive layers and treat them as a single unit, or we can use a fixed bit-width for the weights of layers with lower workload. While this approach may yield sub-optimal solutions, the results are typically satisfactory. To utilize this approach for a given network, we can set the *max_acc_drop* variable to *None*.
<p align="center">
<img src="https://github.com/alexmr09/ISA-extensions-for-Multi-Pumped-Soft-SIMD-Operations/blob/main/assets/figures/pareto_sols.png" width="65%">
</p>
2. In the second case, the user sets the maximum allowable accuracy degradation. We utilize a binary search algorithm across a pre-sorted array of all potential model configurations, ordered by their projected latencies. This approach significantly enhances efficiency by examining merely `log2(3^L)` configurations, swiftly identifying a solution that conforms to the user's accuracy requirements. To utilize this approach for a specific network we need to set the *max_acc_drop* variable to a specific value.
Finally, once the optimal configuration aligning with our constraints is determined, we proceed to automatically generate the files that will be utilized for the inference (and simulation) of the QNN on our extended RISC-V core. More specifically, we will create files that contain:
- The weights and bias values for each layer.
- The scale values for the conversion of the 32-bit accumulated results back to 8-bits. The mathematical equation for this procedure is described on [[1]](#1).
- The C code delineating the functionality of the Quantized Network.
Comprehensive examples that implement the procedure, described above, are provided in this [subfolder](https://github.com/alexmr09/ISA-extensions-for-Multi-Pumped-Soft-SIMD-Operations/tree/main/mpq).
## RISC-V Architecture
### Ibex RISC-V Core
The base design utilized in this work is a generic microarchitecture
implementation of the Ibex, an open-source 32 bit RISC-V CPU
core written in SystemVerilog. Ibex was initially developed as part of the [PULP platform](https://www.pulp-platform.org)
under the name ["Zero-riscy"](https://doi.org/10.1109/PATMOS.2017.8106976), and has been
contributed to [lowRISC](https://www.lowrisc.org) who maintains it and develops it further. It is
under active development.
The CPU core is heavily parametrizable and well suited for
embedded control applications. Ibex is being extensively verified and has
seen multiple tape-outs. Ibex supports the Integer (I) or Embedded (E),
Integer Multiplication and Division (M), Compressed (C), and B (Bit
Manipulation) extensions.
<p align="center">
<img src="https://github.com/alexmr09/ISA-extensions-for-Multi-Pumped-Soft-SIMD-Operations/blob/main/assets/figures/ibex_page-0001.jpg" width="50%">
</p>
You can explore the codebase for the Ibex repository on GitHub by visiting [lowRISC/ibex](https://github.com/lowRISC/ibex).
### Modifications on the Ibex Core
#### Decoder extensions for Mixed-precision
Given that the system’s decoder is initially not configured to recognize the newly introduced instructions, modifications to the decoder are imperative, alongside the integration of the accelerator. By updating the decoder, we ensure it can accurately interpret the opcode and function code fields of these new instructions. This modification enables the decoder to correctly identify and differentiate the new instructions, extract the necessary values from the source registers, and subsequently feed forward this information to the newly added unit.
#### Mixed precision Arithmetic Logic Unit Design
The overarching objective is to amplify the throughput of MAC operations per cycle, a critical metric for computational efficiency in NN processing, while simultaneously minimizing resource utilization and power consumption. These optimizations will enable us to activate the system’s prefetcher and utilize the advanced optimization flags of the GCC compiler resulting in the generation of faster and more efficient code, without having to stall the processor’s pipeline. The most notable ones are:
- The exploitation of the processor's resource, and more specifically its multipliers
- The use of a pipeline inside the structure of the unit to make the system more robust and increase throughput.
- **Multi-Pumping**: We utilize a clock of double frequency for the implementation of the components with the heavier workload.
- **Soft SIMD** : We pack 2 multiplications inside a single multiplier, when asked to calculate the products between 2-bit weights and the 8-bit inputs of each layer.
<p align="center">
<img src="https://github.com/alexmr09/ISA-extensions-for-Multi-Pumped-Soft-SIMD-Operations/blob/main/assets/figures/micro_page-0001.jpg" width="50%">
</p>
## Inference Simulation Using Verilator
For the simulation of our QNNs on the modified Ibex core, with Verilator, we can build and test either:
- [Ibex Simple System](https://github.com/lowRISC/ibex/tree/master/examples/simple_system), which an Ibex based system that can run stand-alone binaries and contains the core, a single memory for instructions and data, and a basic peripheral to write ASCII output.
- [Ibex Demo System](https://github.com/lowrisc/ibex-demo-system), which is an example RISC-V SoC targeting the Arty-A7 FPGA board that includes core alongside UART, GPIO, PWM, Timer, SPI and debug support.
All the necessary files for the 2 designs are located on the [extended_ibex](https://github.com/alexmr09/ISA-extensions-for-Multi-Pumped-Soft-SIMD-Operations/tree/main/extended_ibex) folder.
### Building Simulation
#### Prerequisites
- [Verilator](https://www.veripool.org/verilator/) (we recommend building version 5.008). In brief to install from git:
```
# Prerequisites:
sudo apt-get install git help2man perl python3 make autoconf g++ flex bison ccache
sudo apt-get install libgoogle-perftools-dev numactl perl-doc
sudo apt-get install libelf-dev
sudo apt-get install srecord
sudo apt-get install libfl2 # Ubuntu only (ignore if gives error)
sudo apt-get install libfl-dev # Ubuntu only (ignore if gives error)
sudo apt-get install zlibc zlib1g zlib1g-dev # Ubuntu only (ignore if gives error)
git clone http://git.veripool.org/git/verilator
# Every time you need to build:
unsetenv VERILATOR_ROOT # For csh; ignore error if on bash
unset VERILATOR_ROOT # For bash
cd verilator
git pull # Make sure we're up-to-date
git checkout v5.008
autoconf
./configure
make -j$(nproc)
sudo make install
```
At the end you can ensure that Verilator was successfully installed by checking its version:
```
verilator --version
```
The output should be the following:
```
Verilator 5.008 2023-03-04 rev v5.008
```
- [FuseSoC](https://github.com/olofk/fusesoc), an award-winning package manager and a set of build tools for HDL (Hardware Description Language) code, to automate the process of building the simulations. Ibex uses a [custom fork](https://github.com/lowRISC/fusesoc/tree/ot) of FuseSoC, so we must install it via this method rather than installing FuseSoC separately. For project dependencies, it is more appropriate to use a virtual environment:
```
python3 -m venv .venv
source .venv/bin/activate
pip3 install -U -r python-requirements.txt
```
To build the simulation for the Simple System, run from its directory the following command (while still being inside the virtual environment):
```
cd extended_ibex/ibex_simple_system/
fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system --RV32E=0 --RV32M=ibex_pkg::RV32MSingleCycle
```
Similarly, in order to build the simulation for the Demo System (the one that we will mapped on the FPGA device) run from its directory the following:
```
cd extended_ibex/ibex_demo_system/
fusesoc --cores-root=. run --target=sim --tool=verilator --setup --build lowrisc:ibex:demo_system
```
When we are done, we can deactivate the virtual environment by running:
```
deactivate
```
### Building Software
To compile the appropriate C executable for our Quantized Neural Network, we should first make sure that the previously generated C file along with the header files containing the compressed network's parameters and inputs are located in the same folder under the [inference codes](https://github.com/alexmr09/ISA-extensions-for-Multi-Pumped-Soft-SIMD-Operations/tree/main/inference_codes) directory. Within this directory, you'll find compatible software examples that work for both system simulations.
Additionally on the [common](https://github.com/alexmr09/ISA-extensions-for-Multi-Pumped-Soft-SIMD-Operations/tree/main/inference_codes/common) subfolder, you'll find the optimized kernels featuring the custom instructions.
For example, to build the LeNet5 MNIST example, from our root repository run:
```
make -C inference_codes/lenet5_mnist/optimized
```
The compiled .elf program is available at [inference codes/lenet5_mnist/optimized](https://github.com/alexmr09/ISA-extensions-for-Multi-Pumped-Soft-SIMD-Operations/tree/main/inference_codes/lenet5_mnist/optimized). The same directory also contains a Verilog memory file (vmem file) to be used with some simulators.
### Running the Simulator
Having built the simulator and software, to simulate using Verilator we can use the following commands.
`<sw_elf_file>` should be a path to an ELF file (or alternatively a vmem file)
built as described above. Pass `-t` to get an VCD trace of the execution.
```
# For the Simple System Simuation:
./extended_ibex/ibex_simple_system/build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/Vibex_simple_system [-t] --meminit=ram,<sw_elf_file>
# For the Demo System Simulation:
./extended_ibex/ibex_demo_system/build/lowrisc_ibex_demo_system_0/sim-verilator/Vibex_demo_system [-t] --meminit=ram,<sw_elf_file>
# For example :
./extended_ibex/ibex_demo_system/build/lowrisc_ibex_demo_system_0/sim-verilator/Vibex_demo_system \
--meminit=ram,./inference_codes/lenet5_mnist/optimized/lenet5_mnist.elf
```
We can utilize the simulation output to extract measurements about the latency of our program and estimate speedup with respect to the original Ibex core.
```
Simulation statistics
=====================
Executed cycles: 488901
Wallclock time: 12.188 s
Simulation speed: 40113.3 cycles/s (40.1133 kHz)
Performance Counters
====================
Cycles: 480856
NONE: 0
Instructions Retired: 334753
LSU Busy: 121484
Fetch Wait: 2168
Loads: 117569
Stores: 3915
Jumps: 7
Conditional Branches: 45792
Taken Conditional Branches: 8224
Compressed Instructions: 43
Multiply Wait: 0
Divide Wait: 0
```
## References
<a name="1"> [1] </a> Benoit Jacob, Skirmantas Kligys, Bo Chen, Menglong Zhu, Matthew Tang, Andrew
Howard, Hartwig Adam, and Dmitry Kalenichenko. Quantization and training of
neural networks for efficient integer-arithmetic-only inference, 2017.
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
extended_ibex/ibex_demo_system/data/ibex.svd
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<?xml version="1.0" encoding="utf-8"?>
<!--
Copyright lowRISC contributors.
Licensed under the Apache License, Version 2.0, see LICENSE for details.
SPDX-License-Identifier: Apache-2.0
-->
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
<vendor>lowRISC</vendor>
<name>Ibex Demo System</name>
<version>0.1</version>
<description>
Single-core 3-stage pipeline RISC-V processor,
128 KiB on-chip SRAM\n
1 x UART, 1 x SPI controller, 1 x PWM channels\n
</description>
<licenseText>
Copyright lowRISC contributors.\n
Licensed under the Apache License, Version 2.0, see LICENSE for details.\n
SPDX-License-Identifier: Apache-2.0\n
</licenseText>
<cpu>
<name>Ibex</name>
<revision>r0p1</revision>
<endian>little</endian>
<mpuPresent>false</mpuPresent>
<fpuPresent>false</fpuPresent>
<vtorPresent>1</vtorPresent>
<nvicPrioBits>2</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
<deviceNumInterrupts>1</deviceNumInterrupts>
</cpu>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<peripherals>
<peripheral>
<name>UART0</name>
<version>1</version>
<baseAddress>0x80001000</baseAddress>
<size>32</size>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART0_IRQ</name>
<value>1</value>
</interrupt>
<registers>
<register>
<name>RX</name>
<description>Rx register, UART_RX</description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATA</name>
<description>Receive (read) data character. Transmit (write) data character.</description>
<bitRange>[7:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TX</name>
<description>Tx register, UART_TX</description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATA</name>
<description>Transmit (write) data character.</description>
<bitRange>[7:0]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>Uart Status Register, UART_STATUS</description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_FULL</name>
<description>1 indicates that the TX FIFO is full.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>RX_EMPTY</name>
<description>1 indicates that the RX FIFO is empty.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SPI0</name>
<version>1</version>
<baseAddress>0x80004000</baseAddress>
<size>32</size>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SPI0_IRQ</name>
<value>18</value>
</interrupt>
<registers>
<register>
<name>TX</name>
<description>Tx register, SPI_TX</description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATA</name>
<description>Transmit (write) data character.</description>
<bitRange>[7:0]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>SPI Status Register, SPI_STATUS</description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_EMPTY</name>
<description>1 indicates that the TX FIFO is empty.</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
</field>
<field>
<name>TX_FULL</name>
<description>1 indicates that the TX FIFO is full.</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PWM0</name>
<version>1</version>
<description>Simple PWM0</description>
<baseAddress>0x80003000</baseAddress>
<size>32</size>
<addressBlock>
<offset>0</offset>
<size>0x08</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PWM_IRQ_WRAP</name>
<value>4</value>
</interrupt>
<registers>
<register>
<name>WIDTH</name>
<description>PWM width</description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VALUE</name>
<description>Pwm width.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>COUNTER</name>
<description>PWM counter</description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VALUE</name>
<description>Pwm counter.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="PWM0">
<name>PWM1</name>
<baseAddress>0x8000A008</baseAddress>
<interrupt>
<name>PWM1_IRQ_WRAP</name>
<value>22</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="PWM0">
<name>PWM2</name>
<baseAddress>0x80003010</baseAddress>
<interrupt>
<name>PWM2_IRQ_WRAP</name>
<value>21</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="PWM0">
<name>PWM3</name>
<baseAddress>0x80003018</baseAddress>
<interrupt>
<name>PWM3_IRQ_WRAP</name>
<value>21</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="PWM0">
<name>PWM4</name>
<baseAddress>0x80003020</baseAddress>
<interrupt>
<name>PWM4_IRQ_WRAP</name>
<value>21</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="PWM0">
<name>PWM5</name>
<baseAddress>0x80003028</baseAddress>
<interrupt>
<name>PWM5_IRQ_WRAP</name>
<value>21</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="PWM0">
<name>PWM6</name>
<baseAddress>0x80003030</baseAddress>
<interrupt>
<name>PWM6_IRQ_WRAP</name>
<value>21</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="PWM0">
<name>PWM7</name>
<baseAddress>0x80003038</baseAddress>
<interrupt>
<name>PWM7_IRQ_WRAP</name>
<value>21</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="PWM0">
<name>PWM8</name>
<baseAddress>0x80003040</baseAddress>
<interrupt>
<name>PWM8_IRQ_WRAP</name>
<value>21</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="PWM0">
<name>PWM9</name>
<baseAddress>0x80003048</baseAddress>
<interrupt>
<name>PWM9_IRQ_WRAP</name>
<value>21</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="PWM0">
<name>PWM10</name>
<baseAddress>0x80003050</baseAddress>
<interrupt>
<name>PWM10_IRQ_WRAP</name>
<value>21</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="PWM0">
<name>PWM11</name>
<baseAddress>0x80003058</baseAddress>
<interrupt>
<name>PWM11_IRQ_WRAP</name>
<value>21</value>
</interrupt>
</peripheral>
<peripheral>
<name>TIMER0</name>
<version>1</version>
<description>Controls timer</description>
<baseAddress>0x80002000</baseAddress>
<size>32</size>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIMER_IRQ_0</name>
<value>7</value>
</interrupt>
<registers>
<register>
<name>MTIMEL</name>
<description>mtime low</description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VALUE</name>
<description>mtime low</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MTIMEH</name>
<description>mtime high</description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VALUE</name>
<description>mtime high</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MTIMECMPL</name>
<description>mtime cmp low</description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VALUE</name>
<description>mtime cmp low</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MTIMECMPH</name>
<description>mtime cmp high</description>
<addressOffset>0x000C</addressOffset>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VALUE</name>
<description>mtime cmp high</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOA</name>
<version>1</version>
<description>Gpio port a</description>
<baseAddress>0x80000000</baseAddress>
<size>32</size>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>GPIOA_IRQ</name>
<value>0</value>
</interrupt>
<registers>
<register>
<name>OUT</name>
<description>Write to control the gpio state</description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PINS</name>
<description>Pins.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IN</name>
<description>Read the gpio state</description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PINS</name>
<description>Pins.</description>
<bitRange>[31:0]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IN_DBNC</name>
<description>DBNC</description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VALUE</name>
<description>DBNC.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OUT_SHIFT</name>
<description>Shift register</description>
<addressOffset>0x000C</addressOffset>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VALUE</name>
<description>Shift.</description>
<bitRange>[31:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>
extended_ibex/ibex_demo_system/data/lowrisc.art
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extended_ibex/ibex_demo_system/data/pins_artya7.xdc
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## Based on https://github.com/Digilent/digilent-xdc/blob/master/Arty-A7-100-Master.xdc
## This file is a general .xdc for the Arty A7-100 Rev. D
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
## Clock signal
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { IO_CLK }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { IO_CLK }];
## Switches
set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
## RGB LEDs
set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[0] }]; #IO_L18N_T2_35 Sch=led0_b
set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[1] }]; #IO_L19N_T3_VREF_35 Sch=led0_g
set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[2] }]; #IO_L19P_T3_35 Sch=led0_r
set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[3] }]; #IO_L20P_T3_35 Sch=led1_b
set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[4] }]; #IO_L21P_T3_DQS_35 Sch=led1_g
set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[5] }]; #IO_L20N_T3_35 Sch=led1_r
set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[6] }]; #IO_L21N_T3_DQS_35 Sch=led2_b
set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[7] }]; #IO_L22N_T3_35 Sch=led2_g
set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[8] }]; #IO_L22P_T3_35 Sch=led2_r
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[9] }]; #IO_L23P_T3_35 Sch=led3_b
set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[10] }]; #IO_L24P_T3_35 Sch=led3_g
set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[11] }]; #IO_L23N_T3_35 Sch=led3_r
## LEDs
set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L24N_T3_35 Sch=led[4]
set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_25_35 Sch=led[5]
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
## Buttons
set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { BTN[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { BTN[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { BTN[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { BTN[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
## Pmod Header JA
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1]
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4P_T0_15 Sch=ja[2]
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L4N_T0_15 Sch=ja[3]
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L6P_T0_15 Sch=ja[4]
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L6N_T0_VREF_15 Sch=ja[7]
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8]
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9]
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_25_15 Sch=ja[10]
## Pmod Header JB
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2]
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3]
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3]
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4]
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4]
## Pmod Header JC
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1]
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1]
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2]
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2]
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3]
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3]
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4]
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
## Pmod Header JD
#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { JTAG_TDO }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { JTAG_TRST_N }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { JTAG_TCK }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
##set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { JTAG_TDI }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { JTAG_TMS }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JTAG_RESET_N }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
#set_property PULLUP true [get_ports { JTAG_TRST_N }];
#set_property PULLUP true [get_ports { JTAG_TCK }];
#set_property PULLUP true [get_ports { JTAG_TDI }];
#set_property PULLUP true [get_ports { JTAG_TMS }];
#set_property PULLUP true [get_ports { JTAG_RESET_N }];
## USB-UART Interface
set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { UART_TX }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { UART_RX }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
## ChipKit Outer Digital Header
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0]
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1]
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L8N_T1_D12_14 Sch=ck_io[2]
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3]
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L5P_T0_D06_14 Sch=ck_io[4]
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8]
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L10P_T1_D14_14 Sch=ck_io[9]
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10]
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11]
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12]
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13]
## ChipKit Inner Digital Header
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26]
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27]
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28]
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_25_14 Sch=ck_io[29]
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_0_14 Sch=ck_io[30]
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L5N_T0_D07_14 Sch=ck_io[31]
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32]
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33]
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34]
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35]
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_D11_14 Sch=ck_io[36]
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37]
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L7N_T1_D10_14 Sch=ck_io[38]
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L7P_T1_D09_14 Sch=ck_io[39]
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40]
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
## WARNING: Do not use both sets of constraints at the same time!
## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vaux4_n }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0] ChipKit pin=A0
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vaux4_p }]; #IO_L1P_T0_AD4P_35 Sch=ck_an_p[0] ChipKit pin=A0
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1] ChipKit pin=A1
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1] ChipKit pin=A1
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L7N_T1_AD6N_35 Sch=ck_an_n[2] ChipKit pin=A2
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L7P_T1_AD6P_35 Sch=ck_an_p[2] ChipKit pin=A2
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { vaux7_n }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3] ChipKit pin=A3
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { vaux7_p }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3] ChipKit pin=A3
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L10N_T1_AD15N_35 Sch=ck_an_n[4] ChipKit pin=A4
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L10P_T1_AD15P_35 Sch=ck_an_p[4] ChipKit pin=A4
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[5] ChipKit pin=A5
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[5] ChipKit pin=A5
## ChipKit Outer Analog Header - as Digital I/O
## NOTE: The following constraints should be used when using these ports as digital I/O.
#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_35 Sch=ck_a[0]
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_35 Sch=ck_a[1]
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_35 Sch=ck_a[2]
#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_35 Sch=ck_a[3]
#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4]
#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5]
## ChipKit Inner Analog Header - as Differential Analog Inputs
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
## WARNING: Do not use both sets of constraints at the same time!
## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] ChipKit pin=A6
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] ChipKit pin=A7
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] ChipKit pin=A8
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] ChipKit pin=A9
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vaux14_p }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] ChipKit pin=A10
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vaux14_n }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] ChipKit pin=A11
## ChipKit Inner Analog Header - as Digital I/O
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { DISP_CTRL[0] }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12]
set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { DISP_CTRL[1] }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12]
set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { DISP_CTRL[2] }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13]
set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { SPI_TX }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13]
set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { SPI_SCK }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14]
set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { DISP_CTRL[3] }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14]
## ChipKit SPI
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { SPI_RX }]; #IO_L17N_T2_35 Sch=ck_miso
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { SPI_TX }]; #IO_L17P_T2_35 Sch=ck_mosi
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SPI_SCK }]; #IO_L18P_T2_35 Sch=ck_sck
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { DISP_CTRL[1] }]; #IO_L16N_T2_35 Sch=ck_ss
## ChipKit I2C
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
## Misc. ChipKit Ports
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { IO_RST_N }]; #IO_L16P_T2_35 Sch=ck_rst
## SMSC Ethernet PHY
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
## Quad SPI Flash
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
## Power Measurements
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1]
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1]
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9]
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
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## Clocks
set_property -dict { PACKAGE_PIN N13 IOSTANDARD LVCMOS33 } [get_ports { I_pll_clk1 }];
set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { I_cw_clkin }];
create_clock -period 10.000 -name pll_clk1 -waveform {0.000 5.000} [get_nets I_pll_clk1]
create_clock -period 10.000 -name cw_clkin -waveform {0.000 5.000} [get_nets I_cw_clkin]
## Switches
set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { J16 }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { K16 }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { L14 }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { K15 }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
## LEDs
set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L24N_T3_35 Sch=led[4]
set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_25_35 Sch=led[5]
set_property -dict { PACKAGE_PIN T4 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
set_property DRIVE 8 [get_ports LED*]
## UART
set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { UART_TX }]; #CW IO1
set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { UART_RX }]; #CW IO2
# IO3-4:
set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { IO3 }]; #IO3
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { IO4 }]; #IO4
set_property -dict { PACKAGE_PIN R1 IOSTANDARD LVCMOS33 } [get_ports { IO_RST_N }]; #IO_L16P_T2_35 Sch=ck_rst
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
extended_ibex/ibex_demo_system/data/pins_cw312a35.xdc
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## Clock signal
set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { IO_CLK }]; # HS2 pin
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { IO_CLK }];
## Switches
# IO3-4:
set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { IO3 }]; #IO3
set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { IO4 }]; #IO4
## LEDs
set_property -dict { PACKAGE_PIN R1 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }];
set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }];
set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }];
set_property DRIVE 8 [get_ports LED*]
## UART
set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { UART_TX }]; #CW IO1
set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { UART_RX }]; #CW IO2
set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { IO_RST_N }];
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
extended_ibex/ibex_demo_system/dependencies/edalize.nix
+15
View File
@@ -0,0 +1,15 @@
{ lib, buildPythonPackage, fetchPypi,
jinja2, setuptools_scm, simplesat
}:
buildPythonPackage rec {
pname = "edalize";
version = "0.3.3";
src = fetchPypi {
inherit pname version;
sha256 = "1734aprwzm0z2l60xapqrfxxw747n9h9fflv3n0x4iaradf75abj";
};
SETUPTOOLS_SCM_PRETEND_VERSION = "${version}";
nativeBuildInputs = [ setuptools_scm ];
propagatedBuildInputs = [ jinja2 simplesat ];
doCheck = false;
}
extended_ibex/ibex_demo_system/dependencies/flake.lock
Generated
+63
View File
@@ -0,0 +1,63 @@
{
"nodes": {
"lowrisc_edalize_src": {
"flake": false,
"locked": {
"lastModified": 1649340101,
"narHash": "sha256-iIf7bUBE2SeS/TByUNL9wI1LswlHTmgHYGJltWXNUWE=",
"owner": "lowRISC",
"repo": "edalize",
"rev": "5ae2c3e1ca306e27d81ce5fcc769f62cb7ac42d0",
"type": "github"
},
"original": {
"owner": "lowRISC",
"ref": "ot-0.2",
"repo": "edalize",
"type": "github"
}
},
"lowrisc_fusesoc_src": {
"flake": false,
"locked": {
"lastModified": 1646915773,
"narHash": "sha256-HFrx6vjthNbhrIeV4vNW3YmmqBwqb6lX8lu0dcmQnQM=",
"owner": "lowRISC",
"repo": "fusesoc",
"rev": "c64ca392382b0c432c893d5ce4a93b77af213fdf",
"type": "github"
},
"original": {
"owner": "lowRISC",
"ref": "ot-0.2",
"repo": "fusesoc",
"type": "github"
}
},
"nixpkgs": {
"locked": {
"lastModified": 1673439286,
"narHash": "sha256-CHlGzPceL90wBLD7wt8ZGvulHtf5ZfbXfR37DR10eRs=",
"owner": "nixos",
"repo": "nixpkgs",
"rev": "9c8bff77b5d51380f5da349d0a6fc515da6244b0",
"type": "github"
},
"original": {
"owner": "nixos",
"ref": "nixos-22.11",
"repo": "nixpkgs",
"type": "github"
}
},
"root": {
"inputs": {
"lowrisc_edalize_src": "lowrisc_edalize_src",
"lowrisc_fusesoc_src": "lowrisc_fusesoc_src",
"nixpkgs": "nixpkgs"
}
}
},
"root": "root",
"version": 7
}
extended_ibex/ibex_demo_system/dependencies/flake.nix
+104
View File
@@ -0,0 +1,104 @@
{
description = "ibex simple_system dependencies";
inputs = {
nixpkgs.url = "github:nixos/nixpkgs/nixos-22.11";
lowrisc_fusesoc_src = { url = "github:lowRISC/fusesoc?ref=ot-0.2"; flake = false; };
lowrisc_edalize_src = { url = "github:lowRISC/edalize?ref=ot-0.2"; flake = false; };
};
outputs = {self, nixpkgs,
lowrisc_fusesoc_src, lowrisc_edalize_src,
}:
let
system = "x86_64-linux";
pkgs = import nixpkgs {
inherit system;
config = { allowUnfree = true; };
};
lowRISC_python_overrides = pfinal: pprev: {
fusesoc = pprev.fusesoc.overridePythonAttrs (oldAttrs: {
version = "0.3.3.dev";
src = lowrisc_fusesoc_src;
});
edalize = pprev.edalize.overridePythonAttrs (oldAttrs: {
version = "0.3.3.dev";
src = lowrisc_edalize_src;
});
};
lowRISC_spike_override = final: prev: {
riscv-isa-sim = prev.riscv-isa-sim.overrideAttrs (oldAttrs: rec {
version = "ibex-cosim-v0.3";
src = pkgs.fetchFromGitHub {
owner = "lowrisc";
repo = oldAttrs.pname;
rev = version;
sha256 = "sha256-pKuOpzybOI8UqWV1TSFq4hqTHf7Bft/3WL19fRpwmfU=";
};
});
};
# Using requireFile prevents rehashing each time.
# This saves much seconds during rebuilds.
vivado_bundled_installer_src = pkgs.requireFile rec {
name = "vivado_bundled.tar.gz";
sha256 = "1yxx6crvawhzvary9js0m8bzm35vv6pzfqdkv095r84lb13fyp7b";
# Print the following message if the name / hash are not
# found in the store.
message = ''
requireFile :
file/dir not found in /nix/store
file = ${name}
hash = ${sha256}
This nix expression requires that ${name} is already part of the store.
- Login to xilinx.com
- Download Unified Installer from https://www.xilinx.com/support/download.html,
- Run installer, specify a 'Download Image (Install Seperately)'
- Gzip the bundled installed image directory
- Rename the file to ${name}
- Add it to the nix store with
nix-prefetch-url --type sha256 file:/path/to/${name}
- Change the sha256 key above to $HASH
'';
};
vivado = pkgs.callPackage (import ./vivado.nix) {
# We need to prepare the pre-downloaded installer to
# execute within a nix build. Make use of the included java deps,
# but we still need to do a little patching to make it work.
vivado-src = pkgs.stdenv.mkDerivation rec {
pname = "vivado_src";
version = "2022.2";
src = vivado_bundled_installer_src;
postPatch = ''
patchShebangs .
patchelf \
--set-interpreter $(cat ${pkgs.stdenv.cc}/nix-support/dynamic-linker) \
tps/lnx64/jre*/bin/java
'';
dontBuild = true; dontFixup = true;
installPhase = ''
mkdir -p $out
cp -R * $out
'';
};
};
in
{
overlay_pkgs = pkgs.lib.composeManyExtensions [
(import ./overlay.nix)
lowRISC_spike_override
(final: prev: {
inherit vivado;
})
];
overlay_python = pkgs.lib.composeManyExtensions [
(import ./python-overlay.nix)
lowRISC_python_overrides
];
};
}
extended_ibex/ibex_demo_system/dependencies/fusesoc.nix
+15
View File
@@ -0,0 +1,15 @@
{ lib, buildPythonPackage, fetchPypi,
setuptools_scm, pyparsing, pyyaml, simplesat, ipyxact, edalize
}:
buildPythonPackage rec {
pname = "fusesoc";
version = "1.12.0";
src = fetchPypi {
inherit pname version;
sha256 = "1065arwk1hylf4lqmgqb77fw9izgh7jaib5qnl2dqwdic11c2w44";
};
SETUPTOOLS_SCM_PRETEND_VERSION = "${version}"; # Hack
nativeBuildInputs = [ setuptools_scm ];
propagatedBuildInputs = [ pyparsing pyyaml simplesat ipyxact edalize ];
doCheck = false;
}
extended_ibex/ibex_demo_system/dependencies/ipyxact.nix
+12
View File
@@ -0,0 +1,12 @@
{ lib, buildPythonPackage, fetchPypi,
pyyaml }:
buildPythonPackage rec {
pname = "ipyxact";
version = "0.3.1";
src = fetchPypi {
inherit pname version;
sha256 = "09rv8zn6gqwhdnwgx246mz9biln0q71hsxjf6sb9ilhan75fsn0z";
};
propagatedBuildInputs = [ pyyaml ];
doCheck = false;
}
extended_ibex/ibex_demo_system/dependencies/okonomiyaki.nix
+12
View File
@@ -0,0 +1,12 @@
{ lib, buildPythonPackage, fetchPypi,
attrs, jsonschema, six, zipfile2, distro }:
buildPythonPackage rec {
pname = "okonomiyaki";
version = "1.3.2";
src = fetchPypi {
inherit pname version;
sha256 = "1dw9di7s92z201lwq7aqy5h9h53af73ffx6pnl5iz3lnfi0zf85p";
};
propagatedBuildInputs = [ attrs jsonschema six zipfile2 distro ];
doCheck = false;
}
extended_ibex/ibex_demo_system/dependencies/overlay.nix
+4
View File
@@ -0,0 +1,4 @@
final: prev: {
riscv-gcc-toolchain-lowrisc = prev.callPackage ./riscv-gcc-toolchain-lowrisc.nix {};
riscv-isa-sim = prev.callPackage ./riscv-isa-sim.nix {};
}
extended_ibex/ibex_demo_system/dependencies/python-overlay.nix
+8
View File
@@ -0,0 +1,8 @@
pfinal: pprev: {
ipyxact = pfinal.callPackage ./ipyxact.nix {};
zipfile2 = pfinal.callPackage ./zipfile2.nix {};
simplesat = pfinal.callPackage ./simplesat.nix {};
okonomiyaki = pfinal.callPackage ./okonomiyaki.nix {};
fusesoc = pfinal.callPackage ./fusesoc.nix {};
edalize = pfinal.callPackage ./edalize.nix {};
}
extended_ibex/ibex_demo_system/dependencies/riscv-gcc-toolchain-lowrisc.nix
+32
View File
@@ -0,0 +1,32 @@
{ pkgs, lib, stdenv,
fetchzip, zlib, ncurses5,
}:
# Used for reference...
# https://github.com/NixOS/nixpkgs/blob/master/pkgs/development/compilers/gcc-arm-embedded/10/default.nix
stdenv.mkDerivation rec {
name = "riscv-gcc-toolchain";
version = "20220210-1";
src = fetchzip {
url = "https://github.com/lowRISC/lowrisc-toolchains/releases/download/${version}/lowrisc-toolchain-gcc-rv32imc-${version}.tar.xz";
sha256 = "1m708xfdzf3jzclm2zw51my3nryvlsfwqkgps3xxa0xnhq4ly1bl";
};
dontConfigure = true;
dontBuild = true;
dontPatchELF = true; # We will do this manually in preFixup
dontStrip = true;
installPhase = ''
mkdir -p $out
cp -R * $out
'';
preFixup = ''
find $out -type f ! -name ".o" | while read f; do
patchelf "$f" > /dev/null 2>&1 || continue
patchelf --set-interpreter $(cat ${stdenv.cc}/nix-support/dynamic-linker) "$f" || true
patchelf --set-rpath ${lib.makeLibraryPath [ "$out" stdenv.cc.cc ncurses5 ]} "$f" || true
done
'';
}
extended_ibex/ibex_demo_system/dependencies/riscv-isa-sim.nix
+32
View File
@@ -0,0 +1,32 @@
{ lib, stdenv, fetchFromGitHub,
dtc
}:
stdenv.mkDerivation rec {
name = "spike";
pname = "riscv-isa-sim";
version = "1.1.1-dev";
src = fetchFromGitHub {
owner = "riscv-software-src";
repo = pname;
rev = "ac466a21df442c59962589ba296c702631e041b5";
sha256 = "sha256-1OLGEdj0dGnNREKZOrkAyKET7d2L+VFebOGm2oxtkHw=";
};
enableParallelBuilding = true;
# buildInputs = [ ];
nativeBuildInputs = [ dtc ];
configureFlags = [ "--enable-commitlog" "--enable-misaligned" ];
doCheck = false;
dontInstall = false;
meta = with lib; {
description = "Riscv golden-reference simulator Spike";
homepage = "https://github.com/riscv-software-src/riscv-isa-sim";
license = with licenses; [];
platforms = platforms.unix;
maintainers = with maintainers; [];
};
}
extended_ibex/ibex_demo_system/dependencies/riscv_gcc.nix
+46
View File
@@ -0,0 +1,46 @@
{ # Chosen toolchain subarchitecture, e.g. 'rv32imc'
riscv-arch
# Package set
, pkgs
}:
# --------------------------
# RISC-V GCC Toolchain Setup
let
riscv-toolchain-ver = "8.2.0";
riscv-src = pkgs.fetchFromGitHub {
owner = "lowRISC";
repo = "lowrisc-toolchains";
rev = "2cac2b9797d96a5c46d86d463c71e0a66926f473";
sha256 = "sha256-DNEkdJ5G8wpN2nQbD+nzvAQixWWGCG5RbJrXg5IRteg=";
};
#
# given an architecture like 'rv32i', this will generate the given
# toolchain derivation based on the above source code.
make-riscv-toolchain = arch:
pkgs.stdenv.mkDerivation rec {
name = "riscv-${arch}-toolchain-${version}";
version = "${riscv-toolchain-ver}-${builtins.substring 0 7 src.rev}";
src = riscv-src;
configureFlags = [ "--with-arch=${arch}" ];
installPhase = ":"; # 'make' installs on its own
# installPhase = ''
# mkdir -p $out
# cp -r * $out
# '';
hardeningDisable = [ "all" ];
enableParallelBuilding = true;
# Stripping/fixups break the resulting libgcc.a archives, somehow.
# Maybe something in stdenv that does this...
dontStrip = true;
dontFixup = true;
nativeBuildInputs = with pkgs; [ curl gawk texinfo bison flex gperf ];
buildInputs = with pkgs; [ libmpc mpfr gmp expat ];
};
in make-riscv-toolchain riscv-arch
extended_ibex/ibex_demo_system/dependencies/simplesat.nix
+13
View File
@@ -0,0 +1,13 @@
{ lib, buildPythonPackage, fetchPypi,
okonomiyaki, attrs, six, enum34
}:
buildPythonPackage rec {
pname = "simplesat";
version = "0.8.2";
src = fetchPypi {
inherit pname version;
sha256 = "0n6qm2gzwji19ykp3i6wm6vjw7dnn92h2flm42708fxh6lkz6hqr";
};
propagatedBuildInputs = [ okonomiyaki attrs six enum34 ];
doCheck = false;
}
extended_ibex/ibex_demo_system/dependencies/vivado.nix
+126
View File
@@ -0,0 +1,126 @@
{ stdenv, lib, breakpointHook
, fetchurl, patchelf, makeWrapper
, vivado-src
, coreutils
, procps
, zlib
, ncurses5
, libxcrypt
, libuuid
, libSM
, libICE
, libX11
, libXrender
, libxcb
, libXext
, libXtst
, libXi
, glib
, gtk2
, freetype
}:
stdenv.mkDerivation rec {
pname = "vivado";
version = "2022.2";
# src = vivado-src;
nativeBuildInputs = [
vivado-src
makeWrapper
breakpointHook
];
buildInputs = [
procps
ncurses5
libxcrypt
];
dontUnpack = true;
dontBuild = true;
dontStrip = true;
libPath = lib.makeLibraryPath [
stdenv.cc.cc
ncurses5 zlib libxcrypt
libuuid libSM libICE libX11 libXrender libxcb libXext libXtst libXi
glib gtk2 freetype
];
installPhase = ''
cat <<EOF > install_config.txt
Edition=Vivado ML Standard
Product=Vivado
Destination=$out/opt
Modules=Spartan-7:1,Virtex-7:1,Artix-7:1
InstallOptions=
CreateProgramGroupShortcuts=0
ProgramGroupFolder=Xilinx Design Tools
CreateShortcutsForAllUsers=0
CreateDesktopShortcuts=0
CreateFileAssociation=0
EOF
mkdir -p $out/opt
export LD_LIBRARY_PATH="$LD_LIBRARY_PATH:${libPath}"
export HOME=$out/userhome
# The installer will be killed as soon as it says that post install tasks have failed.
# This is required because it tries to run the unpatched scripts to check if the installation
# has succeeded. However, these scripts will fail because they have not been patched yet,
# and the installer will proceed to delete the installation if not killed.
(${vivado-src}/xsetup \
--agree XilinxEULA,3rdPartyEULA \
--batch Install \
--config install_config.txt || true) | while read line
do
[[ "''${line}" == *"Execution of Pre/Post Installation Tasks Failed"* ]] \
&& echo "killing installer!" \
&& ((pkill -9 -f "tps/lnx64/jre/bin/java") || true)
echo ''${line}
done
'';
preFixup = ''
echo "Patch installed scripts"
patchShebangs $out/opt/Vivado/${version}/bin || true
echo "Hack around lack of libtinfo in NixOS"
ln -s ${ncurses5}/lib/libncursesw.so.6 $out/opt/Vivado/${version}/lib/lnx64.o/libtinfo.so.5 || true
echo "Patch ELFs"
for f in $out/opt/Vivado/${version}/bin/unwrapped/lnx64.o/* \
$out/opt/Vitis_HLS/${version}/bin/unwrapped/lnx64.o/*
do
patchelf --set-interpreter "$(cat ${stdenv.cc}/nix-support/dynamic-linker)" $f || true
done
echo "Wrapping binaries"
for f in $out/opt/Vivado/${version}/bin/vivado \
$out/opt/Vitis_HLS/${version}/bin/vitis_hls
do
wrapProgram $f --prefix LD_LIBRARY_PATH : "${libPath}" || true
done
# 'wrapProgram' on its own does not work
# - This is because of the way the Vivado script runs ./loader
# - Therefore, we need ---Even More Patches...---
echo "Even More Patches..."
sed -i -- 's|`basename "\$0"`|vivado|g' $out/opt/Vivado/$version/bin/.vivado-wrapped
echo "Adding to bin"
mkdir $out/bin
ln -s $out/opt/Vivado/${version}/bin/vivado $out/bin/vivado || true
'';
meta = with lib; {
description = "Xilinx Vivado";
homepage = "https://www.xilinx.com/products/design-tools/vivado.html";
license = licenses.unfree;
};
}
extended_ibex/ibex_demo_system/dependencies/zipfile2.nix
+10
View File
@@ -0,0 +1,10 @@
{ lib, buildPythonPackage, fetchPypi }:
buildPythonPackage rec {
pname = "zipfile2";
version = "0.0.12";
src = fetchPypi {
inherit pname version;
sha256 = "0256m134qs045j1c8mmgii8ipkwhww9sjbc6xyawhykid34zfxkk";
};
doCheck = false;
}
extended_ibex/ibex_demo_system/dv/verilator/demo_system_verilator_lint.vlt
+25
View File
@@ -0,0 +1,25 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// common waiver rules for verilator
`verilator_config
// Do not warn about unconnected pins in module instantiations, e.g.
// `.optional_output ()`.
lint_off -rule PINCONNECTEMPTY
// This warning gives wrong results with blackboxed embedded modules, see
// https://github.com/verilator/verilator/issues/2430
lint_off -rule DECLFILENAME -file "*" -match "Filename '*' does not match NOTFOUNDMODULE name:*"
// Don't generate lint errors for unused parameters in packages. The point is
// that a user of a package might not want to use all of the parameters it
// defines.
lint_off -rule UNUSED -file "*_pkg.sv" -match "*Parameter is not used*"
lint_off -rule UNUSED -file "*pulp_riscv_dbg*" -match "*not used*"
lint_off -rule IMPERFECTSCH -file "*pulp_riscv_dbg*"
lint_off -rule DECLFILENAME -file "*pulp_riscv_dbg*"
lint_off -rule PINMISSING -file "*pulp_riscv_dbg*"
lint_off -rule UNUSED -file "*ibex_register_file_fpga*"
extended_ibex/ibex_demo_system/dv/verilator/ibex_demo_system.cc
+79
View File
@@ -0,0 +1,79 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#include <cassert>
#include <fstream>
#include <iostream>
#include "Vibex_demo_system__Syms.h"
#include "ibex_pcounts.h"
#include "ibex_demo_system.h"
#include "verilated_toplevel.h"
#include "verilator_memutil.h"
#include "verilator_sim_ctrl.h"
DemoSystem::DemoSystem(const char *ram_hier_path, int ram_size_words)
: _ram(ram_hier_path, ram_size_words, 4) {}
int DemoSystem::Main(int argc, char **argv) {
bool exit_app;
int ret_code = Setup(argc, argv, exit_app);
if (exit_app) {
return ret_code;
}
Run();
if (!Finish()) {
return 1;
}
return 0;
}
int DemoSystem::Setup(int argc, char **argv, bool &exit_app) {
VerilatorSimCtrl &simctrl = VerilatorSimCtrl::GetInstance();
simctrl.SetTop(&_top, &_top.clk_sys_i, &_top.clk_sys_fast_i, &_top.rst_sys_ni,
VerilatorSimCtrlFlags::ResetPolarityNegative);
_memutil.RegisterMemoryArea("ram", 0x0, &_ram);
simctrl.RegisterExtension(&_memutil);
exit_app = false;
return simctrl.ParseCommandArgs(argc, argv, exit_app);
}
void DemoSystem::Run() {
VerilatorSimCtrl &simctrl = VerilatorSimCtrl::GetInstance();
std::cout << "Simulation of Ibex Demo System" << std::endl
<< "==============================" << std::endl
<< std::endl;
simctrl.RunSimulation();
}
bool DemoSystem::Finish() {
VerilatorSimCtrl &simctrl = VerilatorSimCtrl::GetInstance();
if (!simctrl.WasSimulationSuccessful()) {
return false;
}
// Set the scope to the root scope, the ibex_pcount_string function otherwise
// doesn't know the scope itself. Could be moved to ibex_pcount_string, but
// would require a way to set the scope name from here, similar to MemUtil.
svSetScope(svGetScopeFromName("TOP.ibex_demo_system"));
std::cout << "\nPerformance Counters" << std::endl
<< "====================" << std::endl;
std::cout << ibex_pcount_string(false);
std::ofstream pcount_csv("ibex_demo_system_pcount.csv");
pcount_csv << ibex_pcount_string(true);
return true;
}
extended_ibex/ibex_demo_system/dv/verilator/ibex_demo_system.h
+23
View File
@@ -0,0 +1,23 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#include "verilated_toplevel.h"
#include "verilator_memutil.h"
class DemoSystem {
public:
DemoSystem(const char *ram_hier_path, int ram_size_words);
virtual ~DemoSystem() {}
virtual int Main(int argc, char **argv);
protected:
ibex_demo_system _top;
VerilatorMemUtil _memutil;
MemArea _ram;
virtual int Setup(int argc, char **argv, bool &exit_app);
virtual void Run();
virtual bool Finish();
};
extended_ibex/ibex_demo_system/dv/verilator/ibex_demo_system_main.cc
+13
View File
@@ -0,0 +1,13 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#include "ibex_demo_system.h"
int main(int argc, char **argv) {
DemoSystem demo_system(
"TOP.ibex_demo_system.u_ram.u_ram.gen_generic.u_impl_generic",
1024 * 1024);
return demo_system.Main(argc, argv);
}
extended_ibex/ibex_demo_system/flake.lock
Generated
+97
View File
@@ -0,0 +1,97 @@
{
"nodes": {
"deps": {
"inputs": {
"lowrisc_edalize_src": "lowrisc_edalize_src",
"lowrisc_fusesoc_src": "lowrisc_fusesoc_src",
"nixpkgs": [
"nixpkgs"
]
},
"locked": {
"lastModified": 1,
"narHash": "sha256-8FX476hjWgbFOzDE+8OUfj8Tv/zJXllOjPnLOY0Adeo=",
"path": "./dependencies",
"type": "path"
},
"original": {
"path": "./dependencies",
"type": "path"
}
},
"flake-utils": {
"locked": {
"lastModified": 1667395993,
"narHash": "sha256-nuEHfE/LcWyuSWnS8t12N1wc105Qtau+/OdUAjtQ0rA=",
"owner": "numtide",
"repo": "flake-utils",
"rev": "5aed5285a952e0b949eb3ba02c12fa4fcfef535f",
"type": "github"
},
"original": {
"owner": "numtide",
"repo": "flake-utils",
"type": "github"
}
},
"lowrisc_edalize_src": {
"flake": false,
"locked": {
"lastModified": 1649340101,
"narHash": "sha256-iIf7bUBE2SeS/TByUNL9wI1LswlHTmgHYGJltWXNUWE=",
"owner": "lowRISC",
"repo": "edalize",
"rev": "5ae2c3e1ca306e27d81ce5fcc769f62cb7ac42d0",
"type": "github"
},
"original": {
"owner": "lowRISC",
"ref": "ot-0.2",
"repo": "edalize",
"type": "github"
}
},
"lowrisc_fusesoc_src": {
"flake": false,
"locked": {
"lastModified": 1646915773,
"narHash": "sha256-HFrx6vjthNbhrIeV4vNW3YmmqBwqb6lX8lu0dcmQnQM=",
"owner": "lowRISC",
"repo": "fusesoc",
"rev": "c64ca392382b0c432c893d5ce4a93b77af213fdf",
"type": "github"
},
"original": {
"owner": "lowRISC",
"ref": "ot-0.2",
"repo": "fusesoc",
"type": "github"
}
},
"nixpkgs": {
"locked": {
"lastModified": 1673439286,
"narHash": "sha256-CHlGzPceL90wBLD7wt8ZGvulHtf5ZfbXfR37DR10eRs=",
"owner": "nixos",
"repo": "nixpkgs",
"rev": "9c8bff77b5d51380f5da349d0a6fc515da6244b0",
"type": "github"
},
"original": {
"owner": "nixos",
"ref": "nixos-22.11",
"repo": "nixpkgs",
"type": "github"
}
},
"root": {
"inputs": {
"deps": "deps",
"flake-utils": "flake-utils",
"nixpkgs": "nixpkgs"
}
}
},
"root": "root",
"version": 7
}
extended_ibex/ibex_demo_system/flake.nix
+158
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@@ -0,0 +1,158 @@
{
description = "Environment for synthesizing and simulating the ibex-demo-system.";
inputs = {
nixpkgs.url = "github:nixos/nixpkgs/nixos-22.11";
flake-utils.url = "github:numtide/flake-utils";
deps = {
url = "path:./dependencies";
inputs.nixpkgs.follows = "nixpkgs";
};
};
outputs = all@{ self, nixpkgs, flake-utils, deps, ... }:
(flake-utils.lib.eachDefaultSystem (system:
let
pkgs = import nixpkgs {
inherit system;
config = { allowUnfree = true; };
overlays =
[ # Add extra packages we might need
# Currently this contains the lowrisc riscv-toolchain, and spike
deps.overlay_pkgs
# Add all the python packages we need that aren't in nixpkgs
# (See the ./dependencies folder for more info)
(final: prev: {
python3 = prev.python3.override {
packageOverrides = deps.overlay_python;
};
})
# Add some missing dependencies to nixpkgs#verilator
(final: prev: {
verilator = prev.verilator.overrideAttrs ( oldAttrs : {
propagatedBuildInputs = [ final.zlib final.libelf ];
});
})
];
};
# Currently we don't build the riscv-toolchain from src, we use a github release
# (See ./dependencies/riscv-gcc-toolchain-lowrisc.nix)
# riscv-toolchain (built from src) # BROKEN
# riscv-gcc-toolchain-lowrisc-src = pkgs.callPackage \
# ./dependencies/riscv_gcc.nix {
# riscv-arch = "rv32imc";
# };
pythonEnv = pkgs.python3.withPackages(ps:
with ps; [ pip fusesoc edalize pyyaml Mako ]
);
# This is the final list of dependencies we need to build the project.
project_deps = [
pythonEnv
] ++ (with pkgs; [
cmake
openocd
screen
verilator
riscv-gcc-toolchain-lowrisc
gtkwave
srecord
openfpgaloader
# vivado
]);
in {
packages.dockertest = pkgs.dockerTools.buildImage {
name = "hello-docker";
copyToRoot = pkgs.buildEnv {
name = "image-root";
paths = [ pkgs.coreutils
pkgs.sl ];
};
config = {
Cmd = [ "${pkgs.sl}/bin/sl" ];
};
};
devShells.default = pkgs.mkShell {
name = "labenv";
buildInputs = project_deps;
shellHook = ''
# FIXME This works on Ubuntu, may not on other distros. FIXME
export LOCALE_ARCHIVE=/usr/lib/locale/locale-archive
# HACK fixup some paths to use our sandboxed python environment
# Currently, fusesoc tries to invoke the program 'python3' from the
# PATH, which when running under a nix python environment, resolves
# to the raw python binary, not wrapped and not including the
# environment's packages. Hence, the first time an import is evaluated
# we will error out.
sed -i -- \
's|interpreter:.*|interpreter: ${pythonEnv}/bin/python3|g' \
vendor/lowrisc_ibex/vendor/lowrisc_ip/dv/tools/ralgen/ralgen.core
sed -i -- \
's|interpreter:.*|interpreter: ${pythonEnv}/bin/python3|g' \
vendor/lowrisc_ibex/vendor/lowrisc_ip/ip/prim/primgen.core
export PS1='labenv(HiPEAC) (ibex-demo-system) \$ '
echo
echo
cat ./data/lowrisc.art
echo "---------------------------------------------------"
echo "Welcome to the 'ibex-demo-system' nix environment!"
echo "---------------------------------------------------"
helpstr=$(cat <<'EOF'
Build ibex software :
mkdir sw/build && pushd sw/build && cmake ../ && make && popd
Build ibex simulation verilator model :
fusesoc --cores-root=. run --target=sim --tool=verilator --setup --build lowrisc:ibex:demo_system
Run ibex simulator verilator model :
./build/lowrisc_ibex_demo_system_0/sim-verilator/Vibex_demo_system -t \
--meminit=ram,sw/build/demo/hello_world/demo
Build ibex-demo-system FPGA bitstream for Arty-A7 :
fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:demo_system
Program Arty-A7 FPGA with bitstream :
openFPGALoader -b arty_a7_35t build/lowrisc_ibex_demo_system_0/synth-vivado/lowrisc_ibex_demo_system_0.bit
Load ibex software to the programmed FPGA :
./util/load_demo_system.sh run ./sw/build/demo/lcd_st7735/lcd_st7735
Start an OpenOCD instance, connected to the Arty-A7 ibex
openocd -f util/arty-a7-openocd-cfg.tcl
Connect gdb to a running program on the FPGA (In a different terminal to the OpenOCD instance):
riscv32-unknown-elf-gdb -ex "target extended-remote localhost:3333" ./sw/build/demo/hello_world/demo
To leave the environment:
exit
EOF
)
helpme(){ echo "$helpstr"; }
helpme
echo
echo "Run 'helpme' in your shell to see this message again."
echo
'';
};
})
) // {
overlay = final: prev: { };
overlays = { exampleOverlay = self.overlay; };
# Utilized by `nix run .#<name>`
# apps.x86_64-linux.hello = {
# type = "app";
# program = c-hello.packages.x86_64-linux.hello;
# };
# Utilized by `nix run . -- <args?>`
# defaultApp.x86_64-linux = self.apps.x86_64-linux.hello;
};
}
extended_ibex/ibex_demo_system/ibex_demo_system.core
+155
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@@ -0,0 +1,155 @@
CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:demo_system"
description: "Ibex Demo System for Arty A7 boards (both, -35 and -100)"
filesets:
files_rtl:
depend:
- lowrisc:ibex:demo_system_core
files_xilinx:
depend:
- lowrisc:ibex:rv_timer
- lowrisc:ibex:fpga_xilinx_shared
files:
- rtl/fpga/top_artya7.sv
file_type: systemVerilogSource
files_xilinx_cw305:
depend:
- lowrisc:ibex:rv_timer
- lowrisc:ibex:fpga_xilinx_shared
files:
- rtl/fpga/top_cw305.sv
file_type: systemVerilogSource
files_xilinx_cw312a35:
depend:
- lowrisc:ibex:rv_timer
- lowrisc:ibex:fpga_xilinx_shared
files:
- rtl/fpga/top_cw312a35.sv
file_type: systemVerilogSource
files_verilator:
depend:
- lowrisc:ibex:sim_shared
- lowrisc:dv_verilator:memutil_verilator
- lowrisc:dv_verilator:simutil_verilator
- lowrisc:dv_verilator:ibex_pcounts
files:
- dv/verilator/ibex_demo_system.cc: { file_type: cppSource }
- dv/verilator/ibex_demo_system.h: { file_type: cppSource, is_include_file: true}
- dv/verilator/ibex_demo_system_main.cc: { file_type: cppSource }
- dv/verilator/demo_system_verilator_lint.vlt: { file_type: vlt }
files_constraints:
files:
- data/pins_artya7.xdc
file_type: xdc
files_constraints_cw305:
files:
- data/pins_cw305.xdc
file_type: xdc
files_constraints_cw312a35:
files:
- data/pins_cw312a35.xdc
file_type: xdc
parameters:
# XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1
# directory. It's best to pass it as absolute path when invoking fusesoc, e.g.
# --SRAMInitFile=$PWD/sw/led/led.vmem
# XXX: The VMEM file should be added to the sources of the Vivado project to
# make the Vivado dependency tracking work. However this requires changes to
# fusesoc first.
SRAMInitFile:
datatype: str
description: SRAM initialization file in vmem hex format
default: "../../../../../sw/build/blank/blank.vmem"
paramtype: vlogparam
# For value definition, please see ip/prim/rtl/prim_pkg.sv
PRIM_DEFAULT_IMPL:
datatype: str
paramtype: vlogdefine
description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
targets:
default: &default_target
filesets:
- files_rtl
synth:
<<: *default_target
default_tool: vivado
filesets_append:
- files_xilinx
- files_constraints
toplevel: top_artya7
tools:
vivado:
part: "xc7a35tcsg324-1" # Default to Arty A7-35
parameters:
- SRAMInitFile
- PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
synth_cw305:
<<: *default_target
default_tool: vivado
filesets_append:
- files_xilinx_cw305
- files_constraints_cw305
toplevel: top_cw305
tools:
vivado:
part: "xc7a100tftg256-2" # default to a100 part
#part: "xc7a35tftg256-2" # a35 option
parameters:
- SRAMInitFile
- PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
synth_cw312a35:
<<: *default_target
default_tool: vivado
filesets_append:
- files_xilinx_cw312a35
- files_constraints_cw312a35
toplevel: top_cw312a35
tools:
vivado:
part: "xc7a35tcsg324-1"
parameters:
- SRAMInitFile
- PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
sim:
<<: *default_target
default_tool: verilator
filesets_append:
- files_verilator
toplevel: ibex_demo_system
tools:
verilator:
mode: cc
verilator_options:
# Disabling tracing reduces compile times but doesn't have a
# huge influence on runtime performance.
- '--trace'
# - '--trace-fst' # this requires -DVM_TRACE_FMT_FST in CFLAGS below!
- '--trace-structs'
- '--trace-params'
- '--trace-max-array 1024'
# - '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_demo_system"'
- '-CFLAGS "-std=c++11 -Wall -DTOPLEVEL_NAME=ibex_demo_system"'
- '-LDFLAGS "-pthread -lutil -lelf"'
- "-Wall"
- "-Wwarn-IMPERFECTSCH"
# RAM primitives wider than 64bit (required for ECC) fail to build in
# Verilator without increasing the unroll count (see Verilator#1266)
- "--unroll-count 72"
parameters:
- PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric
extended_ibex/ibex_demo_system/ibex_demo_system_core.core
+27
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@@ -0,0 +1,27 @@
CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:demo_system_core"
description: "Ibex Demo System for Arty A7 boards (both, -35 and -100)"
filesets:
files_rtl_demo_system:
depend:
- lowrisc:ibex:ibex_top
- pulp:riscv:debug_module
files:
- rtl/system/ibex_demo_system.sv
- rtl/system/dm_top.sv
- rtl/system/debounce.sv
- rtl/system/gpio.sv
- rtl/system/pwm.sv
- rtl/system/pwm_wrapper.sv
- rtl/system/uart.sv
- rtl/system/spi_host.sv
- rtl/system/spi_top.sv
file_type: systemVerilogSource
targets:
default:
filesets:
- files_rtl_demo_system
extended_ibex/ibex_demo_system/ibex_demo_system_pcount.csv
+13
View File
@@ -0,0 +1,13 @@
Cycles,480856
NONE,0
Instructions Retired,334753
LSU Busy,121484
Fetch Wait,2168
Loads,117569
Stores,3915
Jumps,7
Conditional Branches,45792
Taken Conditional Branches,8224
Compressed Instructions,43
Multiply Wait,0
Divide Wait,0
1 Cycles 480856
2 NONE 0
3 Instructions Retired 334753
4 LSU Busy 121484
5 Fetch Wait 2168
6 Loads 117569
7 Stores 3915
8 Jumps 7
9 Conditional Branches 45792
10 Taken Conditional Branches 8224
11 Compressed Instructions 43
12 Multiply Wait 0
13 Divide Wait 0
extended_ibex/ibex_demo_system/pulp_riscv_dbg.core
+42
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@@ -0,0 +1,42 @@
CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "pulp:riscv:debug_module"
description: "RISC-V Debug Module"
filesets:
files_src:
depend:
- lowrisc:prim:fifo
- lowrisc:prim:clock_inv
files:
- vendor/pulp_riscv_dbg/debug_rom/debug_rom.sv
- vendor/pulp_riscv_dbg/debug_rom/debug_rom_one_scratch.sv
- vendor/pulp_riscv_dbg/src/dm_pkg.sv
- vendor/pulp_riscv_dbg/src/dm_sba.sv
- vendor/pulp_riscv_dbg/src/dm_csrs.sv
- vendor/pulp_riscv_dbg/src/dm_mem.sv
- vendor/pulp_riscv_dbg/src/dmi_cdc.sv
- vendor/pulp_riscv_dbg/src/dmi_jtag.sv
file_type: systemVerilogSource
files_vivado:
files:
- vendor/pulp_riscv_dbg/src/dmi_bscane_tap.sv
file_type: systemVerilogSource
files_verilator:
depend:
# common waivers
- lowrisc:lint:common
files:
- vendor/pulp_riscv_dbg/src/dmi_jtag_tap.sv
file_type: systemVerilogSource
targets:
default:
filesets:
- files_src
- tool_verilator ? (files_verilator)
- tool_vivado ? (files_vivado)
extended_ibex/ibex_demo_system/python-requirements.txt
+15
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@@ -0,0 +1,15 @@
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# Individual Python packages
anytree
mako
pyyaml
wheel
# Development version of edalize until all our changes are upstream
git+https://github.com/lowRISC/edalize.git@ot
# Development version with OT-specific changes
git+https://github.com/lowRISC/fusesoc.git@ot
extended_ibex/ibex_demo_system/rtl/fpga/top_artya7.sv
+56
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@@ -0,0 +1,56 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
// This is the top level SystemVerilog file that connects the IO on the board to the Ibex Demo System.
module top_artya7 (
// These inputs are defined in data/pins_artya7.xdc
input IO_CLK,
input IO_RST_N,
input [ 3:0] SW,
input [ 3:0] BTN,
output [ 3:0] LED,
output [11:0] RGB_LED,
output [3:0] DISP_CTRL,
input UART_RX,
output UART_TX,
input SPI_RX,
output SPI_TX,
output SPI_SCK
);
parameter SRAMInitFile = "";
logic clk_sys, rst_sys_n;
// Instantiating the Ibex Demo System.
ibex_demo_system #(
.GpiWidth(8),
.GpoWidth(8),
.PwmWidth(12),
.SRAMInitFile(SRAMInitFile)
) u_ibex_demo_system (
//input
.clk_sys_i(clk_sys),
.rst_sys_ni(rst_sys_n),
.gp_i({SW, BTN}),
.uart_rx_i(UART_RX),
//output
.gp_o({LED, DISP_CTRL}),
.pwm_o(RGB_LED),
.uart_tx_o(UART_TX),
.spi_rx_i(SPI_RX),
.spi_tx_o(SPI_TX),
.spi_sck_o(SPI_SCK)
);
// Generating the system clock and reset for the FPGA.
clkgen_xil7series clkgen(
.IO_CLK,
.IO_RST_N,
.clk_sys,
.rst_sys_n
);
endmodule
extended_ibex/ibex_demo_system/rtl/fpga/top_cw305.sv
+73
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@@ -0,0 +1,73 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
// This is the top level SystemVerilog file that connects the IO on the board to the Ibex Demo System.
module top_cw305 (
// These inputs are defined in data/pins_cw305.xdc
input logic I_pll_clk1,
input logic I_cw_clkin,
input logic IO_RST_N,
input logic IO3,
input logic J16,
input logic K16,
input logic L14,
input logic K15,
output logic IO4,
output logic [ 2:0] LED,
input logic UART_RX,
output logic UART_TX
);
parameter SRAMInitFile = "";
logic clk_sys, rst_sys_n;
reg [24:0] clock_heartbeat;
assign LED[0] = clock_heartbeat[24];
assign LED[1] = ~UART_RX || ~UART_TX;
assign LED[2] = IO4;
always @(posedge clk_sys) clock_heartbeat <= clock_heartbeat + 25'd1;
// Instantiating the Ibex Demo System.
ibex_demo_system #(
.GpiWidth(5),
.GpoWidth(1),
.PwmWidth(1),
.SRAMInitFile(SRAMInitFile)
) u_ibex_demo_system (
//input
.clk_sys_i(clk_sys),
.rst_sys_ni(rst_sys_n),
.gp_i({IO3, K15, L14, K16, J16}),
.uart_rx_i(UART_RX),
//output
.gp_o(IO4),
.pwm_o(),
.uart_tx_o(UART_TX),
.spi_rx_i(1'b0),
.spi_tx_o(),
.spi_sck_o()
);
// clock source select:
logic chosen_clock;
BUFGMUX_CTRL U_clock_source_select (
.O (chosen_clock),
.I0 (I_pll_clk1),
.I1 (I_cw_clkin),
.S (J16) // J16 selects the clock; 0=on-board PLL, 1=from CW HS2 pin
);
// Generating the system clock and reset for the FPGA.
clkgen_xil7series clkgen(
.IO_CLK (chosen_clock),
.IO_RST_N,
.clk_sys,
.rst_sys_n
);
endmodule
extended_ibex/ibex_demo_system/rtl/fpga/top_cw312a35.sv
+58
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@@ -0,0 +1,58 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
// This is the top level SystemVerilog file that connects the IO on the board to the Ibex Demo System.
module top_cw312a35 (
// These inputs are defined in data/pins_cw305.xdc
input logic IO_CLK,
input logic IO_RST_N,
input logic IO3,
output logic IO4,
output logic [ 2:0] LED,
input logic UART_RX,
output logic UART_TX
);
parameter SRAMInitFile = "";
logic clk_sys, rst_sys_n;
reg [24:0] clock_heartbeat;
assign LED[0] = clock_heartbeat[24];
assign LED[1] = ~UART_RX || ~UART_TX;
assign LED[2] = IO4;
always @(posedge clk_sys) clock_heartbeat <= clock_heartbeat + 25'd1;
// Instantiating the Ibex Demo System.
ibex_demo_system #(
.GpiWidth(1),
.GpoWidth(1),
.PwmWidth(1),
.SRAMInitFile(SRAMInitFile)
) u_ibex_demo_system (
//input
.clk_sys_i(clk_sys),
.rst_sys_ni(rst_sys_n),
.gp_i(IO3),
.uart_rx_i(UART_RX),
//output
.gp_o(IO4),
.pwm_o(),
.uart_tx_o(UART_TX),
.spi_rx_i(1'b0),
.spi_tx_o(),
.spi_sck_o()
);
// Generating the system clock and reset for the FPGA.
clkgen_xil7series clkgen(
.IO_CLK,
.IO_RST_N,
.clk_sys,
.rst_sys_n
);
endmodule
extended_ibex/ibex_demo_system/rtl/system/debounce.sv
+41
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@@ -0,0 +1,41 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
// Maintain a counter that increments whilst the input is in the opposite state
// from the debounced output. If the input remains in that state for a certain
// number of cycles (ClkCount) it is deemed stable and becomes the debounced
// output. If the input changes (i.e. it is bouncing) we reset the counter.
module debounce #(
parameter int unsigned ClkCount = 500
) (
input logic clk_i,
input logic rst_ni,
input logic btn_i,
output logic btn_o
);
logic [$clog2(ClkCount+1)-1:0] cnt_d, cnt_q;
logic btn_d, btn_q;
assign btn_o = btn_q;
always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
if (!rst_ni) begin
cnt_q <= '0;
btn_q <= '0;
end else begin
cnt_q <= cnt_d;
btn_q <= btn_d;
end
end
/* verilator lint_off WIDTH */
assign btn_d = (cnt_q >= ClkCount) ? btn_i : btn_q;
// Clear counter if button input equals stored value or if maximum counter value is reached,
// otherwise increment counter.
/* verilator lint_off WIDTH */
assign cnt_d = (btn_i == btn_q || cnt_q >= ClkCount) ? '0 : cnt_q + 1;
endmodule
extended_ibex/ibex_demo_system/rtl/system/dm_top.sv
+260
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@@ -0,0 +1,260 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
// Top-level debug module (DM)
//
// This module implements the RISC-V debug specification version 0.13,
//
// This toplevel wraps the PULP debug module available from
// https://github.com/pulp-platform/riscv-dbg to match the needs of
// the TL-UL-based lowRISC chip design.
`include "prim_assert.sv"
module dm_top #(
parameter int NrHarts = 1,
parameter logic [31:0] IdcodeValue = 32'h 0000_0001,
parameter int BusWidth = 32
) (
input logic clk_i, // clock
input logic rst_ni, // asynchronous reset active low, connect PoR
// here, not the system reset
input logic testmode_i,
output logic ndmreset_o, // non-debug module reset
output logic dmactive_o, // debug module is active
output logic [NrHarts-1:0] debug_req_o, // async debug request
input logic [NrHarts-1:0] unavailable_i, // communicate whether the hart is unavailable
// (e.g.: power down)
// bus device with debug memory, for an execution based technique
input logic slave_req_i,
input logic slave_we_i,
input logic [BusWidth-1:0] slave_addr_i,
input logic [BusWidth/8-1:0] slave_be_i,
input logic [BusWidth-1:0] slave_wdata_i,
output logic [BusWidth-1:0] slave_rdata_o,
// bus host, for system bus accesses
output logic master_req_o,
output logic [BusWidth-1:0] master_add_o,
output logic master_we_o,
output logic [BusWidth-1:0] master_wdata_o,
output logic [BusWidth/8-1:0] master_be_o,
input logic master_gnt_i,
input logic master_r_valid_i,
input logic [BusWidth-1:0] master_r_rdata_i
);
`ASSERT_INIT(paramCheckNrHarts, NrHarts > 0)
// all harts have contiguous IDs
localparam logic [NrHarts-1:0] SelectableHarts = {NrHarts{1'b1}};
// Debug CSRs
dm::hartinfo_t [NrHarts-1:0] hartinfo;
logic [NrHarts-1:0] halted;
logic [NrHarts-1:0] resumeack;
logic [NrHarts-1:0] haltreq;
logic [NrHarts-1:0] resumereq;
logic clear_resumeack;
logic cmd_valid;
dm::command_t cmd;
logic cmderror_valid;
dm::cmderr_e cmderror;
logic cmdbusy;
logic [dm::ProgBufSize-1:0][31:0] progbuf;
logic [dm::DataCount-1:0][31:0] data_csrs_mem;
logic [dm::DataCount-1:0][31:0] data_mem_csrs;
logic data_valid;
logic [19:0] hartsel;
// System Bus Access Module
logic [BusWidth-1:0] sbaddress_csrs_sba;
logic [BusWidth-1:0] sbaddress_sba_csrs;
logic sbaddress_write_valid;
logic sbreadonaddr;
logic sbautoincrement;
logic [2:0] sbaccess;
logic sbreadondata;
logic [BusWidth-1:0] sbdata_write;
logic sbdata_read_valid;
logic sbdata_write_valid;
logic [BusWidth-1:0] sbdata_read;
logic sbdata_valid;
logic sbbusy;
logic sberror_valid;
logic [2:0] sberror;
logic ndmreset;
dm::dmi_req_t dmi_req;
dm::dmi_resp_t dmi_rsp;
logic dmi_req_valid, dmi_req_ready;
logic dmi_rsp_valid, dmi_rsp_ready;
logic dmi_rst_n;
// static debug hartinfo
localparam dm::hartinfo_t DebugHartInfo = '{
zero1: '0,
nscratch: 2, // Debug module needs at least two scratch regs
zero0: 0,
dataaccess: 1'b1, // data registers are memory mapped in the debugger
datasize: dm::DataCount,
dataaddr: dm::DataAddr
};
for (genvar i = 0; i < NrHarts; i++) begin : gen_dm_hart_ctrl
assign hartinfo[i] = DebugHartInfo;
end
assign ndmreset_o = ndmreset;
dm_csrs #(
.NrHarts ( NrHarts ),
.BusWidth ( BusWidth ),
.SelectableHarts ( SelectableHarts )
) i_dm_csrs (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.testmode_i ( testmode_i ),
.dmi_rst_ni ( dmi_rst_n ),
.dmi_req_valid_i ( dmi_req_valid ),
.dmi_req_ready_o ( dmi_req_ready ),
.dmi_req_i ( dmi_req ),
.dmi_resp_valid_o ( dmi_rsp_valid ),
.dmi_resp_ready_i ( dmi_rsp_ready ),
.dmi_resp_o ( dmi_rsp ),
.ndmreset_o ( ndmreset ),
.dmactive_o ( dmactive_o ),
.hartsel_o ( hartsel ),
.hartinfo_i ( hartinfo ),
.halted_i ( halted ),
.unavailable_i,
.resumeack_i ( resumeack ),
.haltreq_o ( haltreq ),
.resumereq_o ( resumereq ),
.clear_resumeack_o ( clear_resumeack ),
.cmd_valid_o ( cmd_valid ),
.cmd_o ( cmd ),
.cmderror_valid_i ( cmderror_valid ),
.cmderror_i ( cmderror ),
.cmdbusy_i ( cmdbusy ),
.progbuf_o ( progbuf ),
.data_i ( data_mem_csrs ),
.data_valid_i ( data_valid ),
.data_o ( data_csrs_mem ),
.sbaddress_o ( sbaddress_csrs_sba ),
.sbaddress_i ( sbaddress_sba_csrs ),
.sbaddress_write_valid_o ( sbaddress_write_valid ),
.sbreadonaddr_o ( sbreadonaddr ),
.sbautoincrement_o ( sbautoincrement ),
.sbaccess_o ( sbaccess ),
.sbreadondata_o ( sbreadondata ),
.sbdata_o ( sbdata_write ),
.sbdata_read_valid_o ( sbdata_read_valid ),
.sbdata_write_valid_o ( sbdata_write_valid ),
.sbdata_i ( sbdata_read ),
.sbdata_valid_i ( sbdata_valid ),
.sbbusy_i ( sbbusy ),
.sberror_valid_i ( sberror_valid ),
.sberror_i ( sberror )
);
dm_sba #(
.BusWidth ( BusWidth )
) i_dm_sba (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.master_req_o ( master_req_o ),
.master_add_o ( master_add_o ),
.master_we_o ( master_we_o ),
.master_wdata_o ( master_wdata_o ),
.master_be_o ( master_be_o ),
.master_gnt_i ( master_gnt_i ),
.master_r_valid_i ( master_r_valid_i ),
.master_r_rdata_i ( master_r_rdata_i ),
.dmactive_i ( dmactive_o ),
.sbaddress_i ( sbaddress_csrs_sba ),
.sbaddress_o ( sbaddress_sba_csrs ),
.sbaddress_write_valid_i ( sbaddress_write_valid ),
.sbreadonaddr_i ( sbreadonaddr ),
.sbautoincrement_i ( sbautoincrement ),
.sbaccess_i ( sbaccess ),
.sbreadondata_i ( sbreadondata ),
.sbdata_i ( sbdata_write ),
.sbdata_read_valid_i ( sbdata_read_valid ),
.sbdata_write_valid_i ( sbdata_write_valid ),
.sbdata_o ( sbdata_read ),
.sbdata_valid_o ( sbdata_valid ),
.sbbusy_o ( sbbusy ),
.sberror_valid_o ( sberror_valid ),
.sberror_o ( sberror )
);
dm_mem #(
.NrHarts ( NrHarts ),
.BusWidth ( BusWidth ),
.SelectableHarts ( SelectableHarts ),
// The debug module provides a simplified ROM for systems that map the debug ROM to offset 0x0
// on the system bus. In that case, only one scratch register has to be implemented in the core.
// However, we require that the DM can be placed at arbitrary offsets in the system, which
// requires the generalized debug ROM implementation and two scratch registers. We hence set
// this parameter to a non-zero value (inside dm_mem, this just feeds into a comparison with 0).
.DmBaseAddress ( 1 )
) i_dm_mem (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.ndmreset_i ( ndmreset ),
.debug_req_o ( debug_req_o ),
.hartsel_i ( hartsel ),
.haltreq_i ( haltreq ),
.resumereq_i ( resumereq ),
.clear_resumeack_i ( clear_resumeack ),
.halted_o ( halted ),
.resuming_o ( resumeack ),
.cmd_valid_i ( cmd_valid ),
.cmd_i ( cmd ),
.cmderror_valid_o ( cmderror_valid ),
.cmderror_o ( cmderror ),
.cmdbusy_o ( cmdbusy ),
.progbuf_i ( progbuf ),
.data_i ( data_csrs_mem ),
.data_o ( data_mem_csrs ),
.data_valid_o ( data_valid ),
.req_i ( slave_req_i ),
.we_i ( slave_we_i ),
.addr_i ( slave_addr_i ),
.wdata_i ( slave_wdata_i ),
.be_i ( slave_be_i ),
.rdata_o ( slave_rdata_o )
);
// Bound-in DPI module replaces the TAP
`ifndef DMIDirectTAP
// JTAG TAP
dmi_jtag #(
.IdcodeValue ( IdcodeValue )
) dap (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
.testmode_i (testmode_i ),
.dmi_rst_no (dmi_rst_n ),
.dmi_req_o (dmi_req ),
.dmi_req_valid_o (dmi_req_valid),
.dmi_req_ready_i (dmi_req_ready),
.dmi_resp_i (dmi_rsp ),
.dmi_resp_ready_o (dmi_rsp_ready),
.dmi_resp_valid_i (dmi_rsp_valid),
//JTAG
.tck_i (1'b0),
.tms_i (1'b0),
.trst_ni (1'b0),
.td_i (1'b0),
.td_o (),
.tdo_oe_o ()
);
`endif
endmodule
extended_ibex/ibex_demo_system/rtl/system/gpio.sv
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
module gpio #(
GpiWidth = 8,
GpoWidth = 16
) (
input logic clk_i,
input logic rst_ni,
input logic device_req_i,
input logic [31:0] device_addr_i,
input logic device_we_i,
input logic [ 3:0] device_be_i,
input logic [31:0] device_wdata_i,
output logic device_rvalid_o,
output logic [31:0] device_rdata_o,
input logic [GpiWidth-1:0] gp_i,
output logic [GpoWidth-1:0] gp_o
);
localparam int unsigned GPIO_OUT_REG = 32'h0;
localparam int unsigned GPIO_IN_REG = 32'h4;
localparam int unsigned GPIO_IN_DBNC_REG = 32'h8;
logic [11:0] reg_addr;
logic [2:0][GpiWidth-1:0] gp_i_q;
logic [GpiWidth-1:0] gp_i_dbnc;
logic [GpoWidth-1:0] gp_o_d;
logic gp_o_wr_en;
logic gp_i_rd_en_d, gp_i_rd_en_q;
logic gp_i_dbnc_rd_en_d, gp_i_dbnc_rd_en_q;
// instantiate debouncers for all GP inputs
for (genvar i = 0; i < GpiWidth; i++) begin
debounce #(
.ClkCount(500)
) dbnc (
.clk_i,
.rst_ni,
.btn_i(gp_i_q[2][i]),
.btn_o(gp_i_dbnc[i])
);
end
always @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
gp_i_q <= '0;
gp_o <= '0;
device_rvalid_o <= '0;
gp_i_rd_en_q <= '0;
gp_i_dbnc_rd_en_q <= '0;
end else begin
gp_i_q <= {gp_i_q[1:0], gp_i};
if (gp_o_wr_en) begin
gp_o <= gp_o_d;
end
device_rvalid_o <= device_req_i;
gp_i_rd_en_q <= gp_i_rd_en_d;
gp_i_dbnc_rd_en_q <= gp_i_dbnc_rd_en_d;
end
end
// assign gp_o_d regarding to device_be_i and GpoWidth
for (genvar i_byte = 0; i_byte < 4; ++i_byte) begin : g_gp_o_d;
if (i_byte * 8 < GpoWidth) begin : g_gp_o_d_inner
localparam int gpo_byte_end = (i_byte + 1) * 8 <= GpoWidth ? (i_byte + 1) * 8 : GpoWidth;
assign gp_o_d[gpo_byte_end - 1 : i_byte * 8] =
device_be_i[i_byte] ? device_wdata_i[gpo_byte_end - 1 : i_byte * 8] :
gp_o[gpo_byte_end - 1 : i_byte * 8];
end
end
// decode write and read requests
assign reg_addr = device_addr_i[11:0];
assign gp_o_wr_en = device_req_i & device_we_i & (reg_addr == GPIO_OUT_REG[11:0]);
assign gp_i_rd_en_d = device_req_i & ~device_we_i & (reg_addr == GPIO_IN_REG[11:0]);
assign gp_i_dbnc_rd_en_d = device_req_i & ~device_we_i & (reg_addr == GPIO_IN_DBNC_REG[11:0]);
// assign device_rdata_o according to request type
always_comb begin
if (gp_i_dbnc_rd_en_q)
device_rdata_o = {{(32 - GpiWidth){1'b0}}, gp_i_dbnc};
else if (gp_i_rd_en_q)
device_rdata_o = {{(32 - GpiWidth){1'b0}}, gp_i_q[2]};
else
device_rdata_o = {{(32 - GpoWidth){1'b0}}, gp_o};
end
logic unused_device_addr, unused_device_be, unused_device_wdata;
assign unused_device_addr = ^device_addr_i[31:10];
// TODO: Do this more neatly
assign unused_device_be = ^device_be_i;
assign unused_device_wdata = ^device_wdata_i[31:GpoWidth];
endmodule
extended_ibex/ibex_demo_system/rtl/system/ibex_demo_system.sv
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
// The Ibex demo system, which instantiates and connects the following blocks:
// - Memory bus.
// - Ibex top module.
// - RAM memory to contain code and data.
// - GPIO driving logic.
// - UART for serial communication.
// - Timer.
// - Debug module.
// - SPI for driving LCD screen
module ibex_demo_system #(
parameter int GpiWidth = 8,
parameter int GpoWidth = 16,
parameter int PwmWidth = 12,
parameter SRAMInitFile = ""
) (
input logic clk_sys_i,
input logic clk_sys_fast_i,
input logic rst_sys_ni,
input logic [GpiWidth-1:0] gp_i,
output logic [GpoWidth-1:0] gp_o,
output logic [PwmWidth-1:0] pwm_o,
input logic uart_rx_i,
output logic uart_tx_o,
input logic spi_rx_i,
output logic spi_tx_o,
output logic spi_sck_o
);
localparam logic [31:0] MEM_SIZE = 32'hE00000; // 10 MB
localparam logic [31:0] MEM_START = 32'h01000000;
localparam logic [31:0] MEM_MASK = ~(MEM_SIZE-1);
localparam logic [31:0] GPIO_SIZE = 4 * 1024; // 4 KiB
localparam logic [31:0] GPIO_START = 32'h80000000;
localparam logic [31:0] GPIO_MASK = ~(GPIO_SIZE-1);
localparam logic [31:0] DEBUG_START = 32'h1a110000;
localparam logic [31:0] DEBUG_SIZE = 64 * 1024; // 64 KiB
localparam logic [31:0] DEBUG_MASK = ~(DEBUG_SIZE-1);
localparam logic [31:0] UART_SIZE = 4 * 1024; // 4 KiB
localparam logic [31:0] UART_START = 32'h80001000;
localparam logic [31:0] UART_MASK = ~(UART_SIZE-1);
localparam logic [31:0] TIMER_SIZE = 4 * 1024; // 4 KiB
localparam logic [31:0] TIMER_START = 32'h80002000;
localparam logic [31:0] TIMER_MASK = ~(TIMER_SIZE-1);
localparam logic [31:0] PWM_SIZE = 4 * 1024; // 4 KiB
localparam logic [31:0] PWM_START = 32'h80003000;
localparam logic [31:0] PWM_MASK = ~(PWM_SIZE-1);
localparam int PwmCtrSize = 8;
parameter logic [31:0] SPI_SIZE = 1 * 1024; // 1kB
parameter logic [31:0] SPI_START = 32'h80004000;
parameter logic [31:0] SPI_MASK = ~(SPI_SIZE-1);
parameter logic [31:0] SIM_CTRL_SIZE = 1 * 1024; // 1kB
parameter logic [31:0] SIM_CTRL_START = 32'h20000;
parameter logic [31:0] SIM_CTRL_MASK = ~(SIM_CTRL_SIZE-1);
// debug functionality is optional
localparam bit DBG = 1;
localparam int unsigned DbgHwBreakNum = (DBG == 1) ? 2 : 0;
localparam bit DbgTriggerEn = (DBG == 1) ? 1'b1 : 1'b0;
typedef enum int {
CoreD,
DbgHost
} bus_host_e;
typedef enum int {
Ram,
Gpio,
Pwm,
Uart,
Timer,
Spi,
SimCtrl,
DbgDev
} bus_device_e;
localparam int NrDevices = DBG ? 8 : 7;
localparam int NrHosts = DBG ? 2 : 1;
// interrupts
logic timer_irq;
logic uart_irq;
// host and device signals
logic host_req [NrHosts];
logic host_gnt [NrHosts];
logic [31:0] host_addr [NrHosts];
logic host_we [NrHosts];
logic [ 3:0] host_be [NrHosts];
logic [31:0] host_wdata [NrHosts];
logic host_rvalid [NrHosts];
logic [31:0] host_rdata [NrHosts];
logic host_err [NrHosts];
// devices (slaves)
logic device_req [NrDevices];
logic [31:0] device_addr [NrDevices];
logic device_we [NrDevices];
logic [ 3:0] device_be [NrDevices];
logic [31:0] device_wdata [NrDevices];
logic device_rvalid [NrDevices];
logic [31:0] device_rdata [NrDevices];
logic device_err [NrDevices];
// Instruction fetch signals
logic core_instr_req;
logic core_instr_gnt;
logic core_instr_rvalid;
logic [31:0] core_instr_addr;
logic [31:0] core_instr_rdata;
logic core_instr_sel_dbg;
logic mem_instr_req;
logic [31:0] mem_instr_rdata;
logic dbg_instr_req;
logic dbg_slave_req;
logic [31:0] dbg_slave_addr;
logic dbg_slave_we;
logic [ 3:0] dbg_slave_be;
logic [31:0] dbg_slave_wdata;
logic dbg_slave_rvalid;
logic [31:0] dbg_slave_rdata;
// Internally generated resets cause IMPERFECTSCH warnings
/* verilator lint_off IMPERFECTSCH */
logic rst_core_n;
logic ndmreset_req;
logic dm_debug_req;
// Device address mapping
logic [31:0] cfg_device_addr_base [NrDevices];
logic [31:0] cfg_device_addr_mask [NrDevices];
assign cfg_device_addr_base[Ram] = MEM_START;
assign cfg_device_addr_mask[Ram] = MEM_MASK;
assign cfg_device_addr_base[Gpio] = GPIO_START;
assign cfg_device_addr_mask[Gpio] = GPIO_MASK;
assign cfg_device_addr_base[Pwm] = PWM_START;
assign cfg_device_addr_mask[Pwm] = PWM_MASK;
assign cfg_device_addr_base[Uart] = UART_START;
assign cfg_device_addr_mask[Uart] = UART_MASK;
assign cfg_device_addr_base[Timer] = TIMER_START;
assign cfg_device_addr_mask[Timer] = TIMER_MASK;
assign cfg_device_addr_base[Spi] = SPI_START;
assign cfg_device_addr_mask[Spi] = SPI_MASK;
assign cfg_device_addr_base[SimCtrl] = SIM_CTRL_START;
assign cfg_device_addr_mask[SimCtrl] = SIM_CTRL_MASK;
if (DBG) begin : g_dbg_device_cfg
assign cfg_device_addr_base[DbgDev] = DEBUG_START;
assign cfg_device_addr_mask[DbgDev] = DEBUG_MASK;
assign device_err[DbgDev] = 1'b0;
end
// Tie-off unused error signals
assign device_err[Ram] = 1'b0;
assign device_err[Gpio] = 1'b0;
assign device_err[Pwm] = 1'b0;
assign device_err[Uart] = 1'b0;
assign device_err[Spi] = 1'b0;
assign device_err[SimCtrl] = 1'b0;
bus #(
.NrDevices ( NrDevices ),
.NrHosts ( NrHosts ),
.DataWidth ( 32 ),
.AddressWidth ( 32 )
) u_bus (
.clk_i (clk_sys_i),
.rst_ni (rst_sys_ni),
.host_req_i (host_req ),
.host_gnt_o (host_gnt ),
.host_addr_i (host_addr ),
.host_we_i (host_we ),
.host_be_i (host_be ),
.host_wdata_i (host_wdata ),
.host_rvalid_o (host_rvalid ),
.host_rdata_o (host_rdata ),
.host_err_o (host_err ),
.device_req_o (device_req ),
.device_addr_o (device_addr ),
.device_we_o (device_we ),
.device_be_o (device_be ),
.device_wdata_o (device_wdata ),
.device_rvalid_i (device_rvalid),
.device_rdata_i (device_rdata ),
.device_err_i (device_err ),
.cfg_device_addr_base,
.cfg_device_addr_mask
);
assign mem_instr_req =
core_instr_req & ((core_instr_addr & cfg_device_addr_mask[Ram]) == cfg_device_addr_base[Ram]);
assign dbg_instr_req =
core_instr_req & ((core_instr_addr & cfg_device_addr_mask[DbgDev]) == cfg_device_addr_base[DbgDev]);
assign core_instr_gnt = mem_instr_req | (dbg_instr_req & ~device_req[DbgDev]);
always @(posedge clk_sys_i or negedge rst_sys_ni) begin
if (!rst_sys_ni) begin
core_instr_rvalid <= 1'b0;
core_instr_sel_dbg <= 1'b0;
end else begin
core_instr_rvalid <= core_instr_gnt;
core_instr_sel_dbg <= dbg_instr_req;
end
end
assign core_instr_rdata = core_instr_sel_dbg ? dbg_slave_rdata : mem_instr_rdata;
assign rst_core_n = rst_sys_ni & ~ndmreset_req;
ibex_top #(
.RegFile ( ibex_pkg::RegFileFPGA ),
.MHPMCounterNum ( 10 ),
.RV32M ( ibex_pkg::RV32MSingleCycle ),
.ICache ( 1'b1 ),
.ICacheECC ( 1'b1 ),
.BranchPredictor ( 1'b1 ),
.ICacheScramble ( 1'b1 ),
.RV32B ( ibex_pkg::RV32BNone ),
.DbgTriggerEn ( DbgTriggerEn ),
.DbgHwBreakNum ( DbgHwBreakNum ),
.DmHaltAddr ( DEBUG_START + dm::HaltAddress[31:0] ),
.DmExceptionAddr ( DEBUG_START + dm::ExceptionAddress[31:0])
) u_top (
.clk_i (clk_sys_i),
.clk_i_fast (clk_sys_fast_i),
.rst_ni(rst_core_n),
.test_en_i ('b0),
.scan_rst_ni(1'b1),
.ram_cfg_i ('b0),
.hart_id_i(32'b0),
// First instruction executed is at 0x0 + 0x80
.boot_addr_i(32'h01000000),
.instr_req_o (core_instr_req),
.instr_gnt_i (core_instr_gnt),
.instr_rvalid_i (core_instr_rvalid),
.instr_addr_o (core_instr_addr),
.instr_rdata_i (core_instr_rdata),
.instr_rdata_intg_i('0),
.instr_err_i ('0),
.data_req_o (host_req[CoreD]),
.data_gnt_i (host_gnt[CoreD]),
.data_rvalid_i (host_rvalid[CoreD]),
.data_we_o (host_we[CoreD]),
.data_be_o (host_be[CoreD]),
.data_addr_o (host_addr[CoreD]),
.data_wdata_o (host_wdata[CoreD]),
.data_wdata_intg_o(),
.data_rdata_i (host_rdata[CoreD]),
.data_rdata_intg_i('0),
.data_err_i (host_err[CoreD]),
.irq_software_i(1'b0),
.irq_timer_i (timer_irq),
.irq_external_i(1'b0),
.irq_fast_i ({14'b0, uart_irq}),
.irq_nm_i (1'b0),
.scramble_key_valid_i('0),
.scramble_key_i ('0),
.scramble_nonce_i ('0),
.scramble_req_o (),
.debug_req_i (dm_debug_req),
.crash_dump_o (),
.double_fault_seen_o(),
.fetch_enable_i ('1),
.alert_minor_o (),
.alert_major_internal_o(),
.alert_major_bus_o (),
.core_sleep_o ()
);
ram_2p #(
.Depth ( MEM_SIZE / 4 ),
.MemInitFile ( SRAMInitFile )
) u_ram (
.clk_i (clk_sys_i),
.rst_ni (rst_sys_ni),
.a_req_i (device_req[Ram]),
.a_we_i (device_we[Ram]),
.a_be_i (device_be[Ram]),
.a_addr_i (device_addr[Ram]),
.a_wdata_i (device_wdata[Ram]),
.a_rvalid_o (device_rvalid[Ram]),
.a_rdata_o (device_rdata[Ram]),
.b_req_i (mem_instr_req),
.b_we_i (1'b0),
.b_be_i (4'b0),
.b_addr_i (core_instr_addr),
.b_wdata_i (32'b0),
.b_rvalid_o (),
.b_rdata_o (mem_instr_rdata)
);
gpio #(
.GpiWidth ( GpiWidth ),
.GpoWidth ( GpoWidth )
) u_gpio (
.clk_i (clk_sys_i),
.rst_ni (rst_sys_ni),
.device_req_i (device_req[Gpio]),
.device_addr_i (device_addr[Gpio]),
.device_we_i (device_we[Gpio]),
.device_be_i (device_be[Gpio]),
.device_wdata_i (device_wdata[Gpio]),
.device_rvalid_o(device_rvalid[Gpio]),
.device_rdata_o (device_rdata[Gpio]),
.gp_i,
.gp_o
);
pwm_wrapper #(
.PwmWidth ( PwmWidth ),
.PwmCtrSize ( PwmCtrSize ),
.BusWidth ( 32 )
) u_pwm (
.clk_i (clk_sys_i),
.rst_ni (rst_sys_ni),
.device_req_i (device_req[Pwm]),
.device_addr_i (device_addr[Pwm]),
.device_we_i (device_we[Pwm]),
.device_be_i (device_be[Pwm]),
.device_wdata_i (device_wdata[Pwm]),
.device_rvalid_o(device_rvalid[Pwm]),
.device_rdata_o (device_rdata[Pwm]),
.pwm_o
);
uart #(
.ClockFrequency ( 50_000_000 )
) u_uart (
.clk_i (clk_sys_i),
.rst_ni (rst_sys_ni),
.device_req_i (device_req[Uart]),
.device_addr_i (device_addr[Uart]),
.device_we_i (device_we[Uart]),
.device_be_i (device_be[Uart]),
.device_wdata_i (device_wdata[Uart]),
.device_rvalid_o(device_rvalid[Uart]),
.device_rdata_o (device_rdata[Uart]),
.uart_rx_i,
.uart_irq_o (uart_irq),
.uart_tx_o
);
spi_top #(
.ClockFrequency(50_000_000),
.CPOL(0),
.CPHA(1)
) u_spi (
.clk_i (clk_sys_i),
.rst_ni(rst_sys_ni),
.device_req_i (device_req[Spi]),
.device_addr_i (device_addr[Spi]),
.device_we_i (device_we[Spi]),
.device_be_i (device_be[Spi]),
.device_wdata_i (device_wdata[Spi]),
.device_rvalid_o(device_rvalid[Spi]),
.device_rdata_o (device_rdata[Spi]),
.spi_rx_i(spi_rx_i), // Data received from SPI device
.spi_tx_o(spi_tx_o), // Data transmitted to SPI device
.sck_o(spi_sck_o), // Serial clock pin
.byte_data_o() // unused
);
`ifdef VERILATOR
simulator_ctrl #(
.LogName("ibex_demo_system.log")
) u_simulator_ctrl (
.clk_i (clk_sys_i),
.rst_ni (rst_sys_ni),
.req_i (device_req[SimCtrl]),
.we_i (device_we[SimCtrl]),
.be_i (device_be[SimCtrl]),
.addr_i (device_addr[SimCtrl]),
.wdata_i (device_wdata[SimCtrl]),
.rvalid_o (device_rvalid[SimCtrl]),
.rdata_o (device_rdata[SimCtrl])
);
`endif
timer #(
.DataWidth ( 32 ),
.AddressWidth ( 32 )
) u_timer (
.clk_i (clk_sys_i),
.rst_ni (rst_sys_ni),
.timer_req_i (device_req[Timer]),
.timer_we_i (device_we[Timer]),
.timer_be_i (device_be[Timer]),
.timer_addr_i (device_addr[Timer]),
.timer_wdata_i (device_wdata[Timer]),
.timer_rvalid_o(device_rvalid[Timer]),
.timer_rdata_o (device_rdata[Timer]),
.timer_err_o (device_err[Timer]),
.timer_intr_o (timer_irq)
);
assign dbg_slave_req = device_req[DbgDev] | dbg_instr_req;
assign dbg_slave_we = device_req[DbgDev] & device_we[DbgDev];
assign dbg_slave_addr = device_req[DbgDev] ? device_addr[DbgDev] : core_instr_addr;
assign dbg_slave_be = device_be[DbgDev];
assign dbg_slave_wdata = device_wdata[DbgDev];
assign device_rvalid[DbgDev] = dbg_slave_rvalid;
assign device_rdata[DbgDev] = dbg_slave_rdata;
always @(posedge clk_sys_i or negedge rst_sys_ni) begin
if (!rst_sys_ni) begin
dbg_slave_rvalid <= 1'b0;
end else begin
dbg_slave_rvalid <= device_req[DbgDev];
end
end
if (DBG) begin : g_dm_top
dm_top #(
.NrHarts ( 1 )
) u_dm_top (
.clk_i (clk_sys_i),
.rst_ni (rst_sys_ni),
.testmode_i (1'b0),
.ndmreset_o (ndmreset_req),
.dmactive_o (),
.debug_req_o (dm_debug_req),
.unavailable_i (1'b0),
// bus device with debug memory (for execution-based debug)
.slave_req_i (dbg_slave_req),
.slave_we_i (dbg_slave_we),
.slave_addr_i (dbg_slave_addr),
.slave_be_i (dbg_slave_be),
.slave_wdata_i (dbg_slave_wdata),
.slave_rdata_o (dbg_slave_rdata),
// bus host (for system bus accesses, SBA)
.master_req_o (host_req[DbgHost]),
.master_add_o (host_addr[DbgHost]),
.master_we_o (host_we[DbgHost]),
.master_wdata_o (host_wdata[DbgHost]),
.master_be_o (host_be[DbgHost]),
.master_gnt_i (host_gnt[DbgHost]),
.master_r_valid_i (host_rvalid[DbgHost]),
.master_r_rdata_i (host_rdata[DbgHost])
);
end else begin
assign dm_debug_req = 1'b0;
assign ndmreset_req = 1'b0;
end
`ifdef VERILATOR
export "DPI-C" function mhpmcounter_get;
function automatic longint unsigned mhpmcounter_get(int index);
return u_top.u_ibex_core.cs_registers_i.mhpmcounter[index];
endfunction
`endif
endmodule
extended_ibex/ibex_demo_system/rtl/system/pwm.sv
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
module pwm #(
parameter int CtrSize = 8
) (
input logic clk_i,
input logic rst_ni,
// To produce an always-on signal, you will need to make pulse_width_i > max_counter_i.
input logic [CtrSize-1:0] pulse_width_i,
input logic [CtrSize-1:0] max_counter_i,
output logic modulated_o
);
logic [CtrSize-1:0] counter;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
counter <= 'b0;
modulated_o <= 'b0;
end else if (max_counter_i == 0) begin
// Set output to low when maximum is zero.
counter <= 'b0;
modulated_o <= 'b0;
end else begin
// Wrap the counter once it gets to the maximum.
if (counter < max_counter_i) begin
counter <= counter + 1;
end else begin
counter <= 0;
end
// Set output to high for pulse_width_i/max_counter_i amount of time.
if (pulse_width_i > counter) begin
modulated_o <= 1'b1;
end else begin
modulated_o <= 1'b0;
end
end
end
endmodule
extended_ibex/ibex_demo_system/rtl/system/pwm_wrapper.sv
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
// This wrapper instantiates a series of PWMs and distributes requests from the device bus.
module pwm_wrapper #(
parameter int PwmWidth = 12,
parameter int PwmCtrSize = 8,
parameter int BusWidth = 32
) (
input logic clk_i,
input logic rst_ni,
// IO for device bus.
input logic device_req_i,
input logic [BusWidth-1:0] device_addr_i,
input logic device_we_i,
input logic [ 3:0] device_be_i,
input logic [BusWidth-1:0] device_wdata_i,
output logic device_rvalid_o,
output logic [BusWidth-1:0] device_rdata_o,
// Collected output of all PWMs.
output logic [PwmWidth-1:0] pwm_o
);
localparam int unsigned AddrWidth = 10;
localparam int unsigned PwmIdxOffset = $clog2(BusWidth / 8) + 1;
localparam int unsigned PwmIdxWidth = AddrWidth - PwmIdxOffset;
// Generate PwmWidth number of PWMs.
for (genvar i = 0; i < PwmWidth; i++) begin : gen_pwm
logic [PwmCtrSize-1:0] data_d;
logic [PwmCtrSize-1:0] counter_q;
logic [PwmCtrSize-1:0] pulse_width_q;
logic counter_en;
logic pulse_width_en;
logic [PwmIdxWidth-1:0] pwm_idx;
assign pwm_idx = i;
// Byte enables are currently unsupported for PWM.
assign data_d = device_wdata_i[PwmCtrSize-1:0]; // Only take PwmCtrSize LSBs.
// Each PWM has a 64-bit block. The most significant 32 bits are the counter and the least
// significant 32 bits are the pulse width.
assign counter_en = device_req_i & device_we_i
& (device_addr_i[AddrWidth-1:PwmIdxOffset] == pwm_idx)
& device_addr_i[PwmIdxOffset-1];
assign pulse_width_en = device_req_i & device_we_i
& (device_addr_i[AddrWidth-1:PwmIdxOffset] == pwm_idx)
& ~device_addr_i[PwmIdxOffset-1];
always @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
counter_q <= '0;
pulse_width_q <= '0;
end else begin
if (counter_en) begin
counter_q <= data_d;
end
if (pulse_width_en) begin
pulse_width_q <= data_d;
end
end
end
pwm #(
.CtrSize( PwmCtrSize )
) u_pwm (
.clk_i (clk_i),
.rst_ni (rst_ni),
.pulse_width_i(pulse_width_q),
.max_counter_i(counter_q),
.modulated_o (pwm_o[i])
);
end : gen_pwm
// Generating the device bus output.
// Reading from PWM currently not possible.
assign device_rdata_o = 32'b0;
always @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
device_rvalid_o <= 1'b0;
end else begin
// TODO only set rvalid if rdata was valid.
device_rvalid_o <= device_req_i;
end
end
logic _unused;
assign _unused = ^device_be_i ^ ^device_wdata_i;
endmodule
extended_ibex/ibex_demo_system/rtl/system/spi_host.sv
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
module spi_host #(
parameter int unsigned ClockFrequency = 50_000_000,
parameter int unsigned BaudRate = 12_500_000,
parameter bit CPOL = 0,
parameter bit CPHA = 0
)(
input clk_i,
input rst_ni,
input logic spi_rx_i,
output logic spi_tx_o,
output logic sck_o,
input logic start_i,
input logic [7:0] byte_data_i,
output logic [7:0] byte_data_o,
output logic next_tx_byte_o
);
// ClocksPerBaud: Clock cycles in between two SPI SCLK cycles (DEFAULT:4)
localparam int unsigned ClocksPerBaud = ClockFrequency / BaudRate;
// ToggleCount: The point which SCK would toggle (DEFAULT:2)
localparam int unsigned ToggleCount = ClocksPerBaud / 2;
// CountWidth: Width of the implemented counter for generating SCK (DEFAULT:1)
localparam int unsigned CountWidth = $clog2(ToggleCount);
logic [CountWidth-1:0] limit, count;
logic sck, count_at_limit, sck_pos, sck_neg;
logic sck_en;
assign sck_en = (state_q == SEND);
assign limit = CountWidth'(ToggleCount - 1);
assign count_at_limit = (count >= limit);
always_ff @(posedge clk_i or negedge rst_ni) begin
// Do not start clock related logic unless we are starting
// SPI transmission or already at SEND state.
if (!rst_ni) begin
count <= '0;
sck <= CPOL;
end else if (!(sck_en||start_i)) begin
count <= '0;
sck <= CPOL;
// In the case of counter reaching to the limit, toggle SCK and start over.
end else if (count_at_limit) begin
count <= '0;
sck <= ~sck;
end else begin
count <= count + 1'b1;
end
end
// Only send clock to the pad when we are at the SEND state.
assign sck_o = sck_en ? sck : CPOL;
// Set to HIGH at the posedge of the serial clock, used internally.
assign sck_pos = count_at_limit && !sck;
// Set to HIGH at the negedge of the serial clock, used internally.
assign sck_neg = count_at_limit && sck;
typedef enum logic[1:0] {
IDLE,
START,
SEND,
STOP
} spi_state_t;
spi_state_t state_q, state_d;
logic [2:0] bit_counter_q, bit_counter_d;
logic [7:0] current_byte_q, current_byte_d, recieved_byte_d, recieved_byte_q;
always_comb begin
spi_tx_o = 1'b1;
bit_counter_d = bit_counter_q;
current_byte_d = current_byte_q;
next_tx_byte_o = 1'b0;
state_d = state_q;
byte_data_o = '0;
case (state_q)
IDLE: begin
spi_tx_o = 1'b1;
if (start_i) begin
state_d = START;
end
end
START: begin
state_d = SEND;
bit_counter_d = 3'd7;
current_byte_d = byte_data_i;
end
SEND: begin
spi_tx_o = current_byte_q[7];
current_byte_d = {current_byte_q[6:0], 1'b0};
if (bit_counter_q == 3'd0) begin
state_d = STOP;
end else begin
bit_counter_d = bit_counter_q - 3'd1;
end
end
STOP: begin
spi_tx_o = 1'b1;
next_tx_byte_o = 1'b1;
byte_data_o = recieved_byte_q;
state_d = IDLE;
end
endcase
end
generate
// If CPHA is HIGH, incoming data will be sampled on the falling edge while outgoing
// data will get shifted out on the rising edge.
if (CPHA) begin
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
current_byte_q <= '0;
bit_counter_q <= '0;
recieved_byte_q <= '0;
state_q <= IDLE;
end else if (sck_pos) begin
bit_counter_q <= bit_counter_d;
recieved_byte_q <= recieved_byte_d;
state_q <= state_d;
// Set current byte half a cycle before transmitting it.
end else if (sck_neg) begin
current_byte_q <= current_byte_d;
if (state_q == SEND) begin
recieved_byte_d <= {recieved_byte_q[6:0], spi_rx_i};
end
end
end
// If CPHA is LOW, incoming data will be sampled on the rising edge while outgoing
// data will get shifted out on the falling edge.
end else begin
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
current_byte_q <= '0;
bit_counter_q <= '0;
recieved_byte_q <= '0;
state_q <= IDLE;
// Set current byte half a cycle before transmitting it.
end else if (sck_pos) begin
current_byte_q <= current_byte_d;
if (state_q == SEND) begin
recieved_byte_d <= {recieved_byte_q[6:0], spi_rx_i};
end
end else if (sck_neg) begin
bit_counter_q <= bit_counter_d;
recieved_byte_q <= recieved_byte_d;
state_q <= state_d;
end
end
end
endgenerate
endmodule
extended_ibex/ibex_demo_system/rtl/system/spi_top.sv
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
module spi_top #(
parameter int unsigned ClockFrequency = 50_000_000,
parameter int unsigned BaudRate = 12_500_000,
parameter CPOL = 0,
parameter CPHA = 0
) (
input logic clk_i,
input logic rst_ni,
input logic device_req_i,
/* verilator lint_off UNUSED */
input logic [31:0] device_addr_i,
input logic device_we_i,
/* verilator lint_off UNUSED */
input logic [3:0] device_be_i,
/* verilator lint_off UNUSED */
input logic [31:0] device_wdata_i,
output logic device_rvalid_o,
output logic [31:0] device_rdata_o,
input logic spi_rx_i,
output logic spi_tx_o,
output logic sck_o,
output logic [7:0] byte_data_o
);
localparam logic [11:0] SPI_TX_REG = 12'h0;
localparam logic [11:0] SPI_STATUS_REG = 12'h4;
logic [11:0] reg_addr;
// Status register read enable
logic read_status_q, read_status_d;
// Edge detection for popping FIFO elements.
logic next_tx_byte_d, next_tx_byte_q;
logic tx_fifo_wvalid;
logic tx_fifo_rvalid, tx_fifo_rready;
logic [7:0] tx_fifo_rdata;
logic tx_fifo_full, tx_fifo_empty;
logic [6:0] tx_fifo_depth;
always @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
next_tx_byte_q <= '0;
device_rvalid_o <= '0;
end else begin
next_tx_byte_q <= next_tx_byte_d;
device_rvalid_o <= device_req_i;
end
end
// This is needed because signal arrives in a slower clock.
assign tx_fifo_rready = next_tx_byte_d && ~next_tx_byte_q;
// We have 1kB space for SPI related registers, ignore top address bits.
assign reg_addr = device_addr_i[11:0];
// FIFO depth signal gives the current valid elements in the FIFO, zero means it's empty.
// This will be used in software to indicate whenever we see an empty
assign tx_fifo_empty = (tx_fifo_depth == 0);
// FIFO push happens when software writes to SPI_TX_REG
assign tx_fifo_wvalid = (device_req_i & (reg_addr == SPI_TX_REG) & device_we_i);
assign read_status_d = (device_req_i & (reg_addr == SPI_STATUS_REG) & ~device_we_i);
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
read_status_q <= 0;
end else begin
read_status_q <= read_status_d;
end
end
assign device_rdata_o = read_status_q ? {30'b0, tx_fifo_empty, tx_fifo_full} : 32'b0;
prim_fifo_sync #(
.Width(8),
.Pass(1'b0),
.Depth(127)
) u_tx_fifo (
.clk_i (clk_i),
.rst_ni,
.clr_i(1'b0),
.wvalid_i(tx_fifo_wvalid), // FIFO Push
.wready_o(),
.wdata_i(device_wdata_i[7:0]),
.rvalid_o(tx_fifo_rvalid),
.rready_i(tx_fifo_rready), // FIFO Pop
.rdata_o(tx_fifo_rdata),
.full_o(tx_fifo_full),
.depth_o(tx_fifo_depth),
.err_o() // Unused
);
spi_host #(
.ClockFrequency(ClockFrequency),
.BaudRate(BaudRate),
.CPOL(CPOL),
.CPHA(CPHA)
) u_spi_host (
.clk_i (clk_i),
.rst_ni(rst_ni),
.spi_rx_i(spi_rx_i), // Data received from SPI device
.spi_tx_o(spi_tx_o), // Data transmitted to SPI device
.sck_o(sck_o), // Serial clock output
.start_i(tx_fifo_rvalid), // Starts SPI as long as we have a valid FIFO data.
.byte_data_i(tx_fifo_rdata), // 8-bit data, from FIFO possibly
.byte_data_o(byte_data_o),
.next_tx_byte_o(next_tx_byte_d) // requests new byte
);
endmodule
extended_ibex/ibex_demo_system/rtl/system/uart.sv
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
module uart #(
parameter int unsigned ClockFrequency = 50_000_000,
parameter int unsigned BaudRate = 115_200,
parameter int unsigned RxFifoDepth = 128,
parameter int unsigned TxFifoDepth = 128
) (
input logic clk_i,
input logic rst_ni,
input logic device_req_i,
/* verilator lint_off UNUSED */
input logic [31:0] device_addr_i,
input logic device_we_i,
input logic [3:0] device_be_i,
input logic [31:0] device_wdata_i,
output logic device_rvalid_o,
output logic [31:0] device_rdata_o,
input logic uart_rx_i,
output logic uart_irq_o,
output logic uart_tx_o
);
localparam int unsigned ClocksPerBaud = ClockFrequency / BaudRate;
/* verilator lint_off WIDTH */
localparam int unsigned UART_RX_REG = 32'h0;
/* verilator lint_off WIDTH */
localparam int unsigned UART_TX_REG = 32'h4;
/* verilator lint_off WIDTH */
localparam int unsigned UART_STATUS_REG = 32'h8;
typedef enum logic[1:0] {
IDLE,
START,
PROC,
STOP
} uart_state_t;
logic [31:0] device_rdata_d, device_rdata_q;
logic device_rvalid_d, device_rvalid_q;
logic [11:0] reg_addr;
logic [$clog2(ClocksPerBaud)-1:0] rx_baud_counter_q, rx_baud_counter_d;
logic rx_baud_tick;
uart_state_t rx_state_q, rx_state_d;
logic [2:0] rx_bit_counter_q, rx_bit_counter_d;
logic [7:0] rx_current_byte_q, rx_current_byte_d;
logic [2:0] rx_q;
logic rx_start, rx_valid;
logic rx_fifo_wvalid;
logic rx_fifo_rready;
logic [7:0] rx_fifo_rdata;
logic rx_fifo_rvalid;
logic rx_fifo_empty;
logic [$clog2(ClocksPerBaud)-1:0] tx_baud_counter_q, tx_baud_counter_d;
logic tx_baud_tick;
logic write_req;
uart_state_t tx_state_q, tx_state_d;
logic [2:0] tx_bit_counter_q, tx_bit_counter_d;
logic [7:0] tx_current_byte_q, tx_current_byte_d;
logic tx_next_byte;
logic tx_fifo_wvalid;
logic tx_fifo_rvalid, tx_fifo_rready;
logic [7:0] tx_fifo_rdata;
logic tx_fifo_full;
assign reg_addr = device_addr_i[11:0];
always_comb begin
device_rdata_d = '0;
device_rvalid_d = 1'b0;
rx_fifo_rready = 1'b0;
if (device_req_i) begin
device_rvalid_d = 1'b1;
if (device_be_i[0] & ~device_we_i) begin
case (reg_addr)
UART_RX_REG: begin
device_rdata_d = {24'b0, rx_fifo_rdata};
rx_fifo_rready = 1'b1;
end
UART_TX_REG: begin
device_rdata_d = '0;
end
UART_STATUS_REG: begin
device_rdata_d = {30'b0, tx_fifo_full, rx_fifo_empty};
end
default: begin
device_rdata_d = '0;
end
endcase
end
end
end
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
device_rdata_q <= '0;
device_rvalid_q <= 1'b0;
end else begin
device_rdata_q <= device_rdata_d;
device_rvalid_q <= device_rvalid_d;
end
end
assign device_rdata_o = device_rdata_q;
assign device_rvalid_o = device_rvalid_q;
assign rx_fifo_wvalid = rx_baud_tick & rx_valid;
assign rx_fifo_empty = ~rx_fifo_rvalid;
// Set the rx_baud_counter half-way on rx_start to ensure sampling the bits 'in the middle'
assign rx_baud_counter_d = rx_baud_tick ? '0 :
rx_start ? $bits(rx_baud_counter_q)'(ClocksPerBaud >> 1) :
rx_baud_counter_q + 1'b1;
assign rx_baud_tick = rx_baud_counter_q == $bits(rx_baud_counter_q)'(ClocksPerBaud - 1);
prim_fifo_sync #(
.Width(8),
.Pass (1'b0),
.Depth(RxFifoDepth)
) u_rx_fifo (
.clk_i,
.rst_ni,
.clr_i (1'b0),
.wvalid_i(rx_fifo_wvalid),
.wready_o(),
.wdata_i (rx_current_byte_q),
.rvalid_o(rx_fifo_rvalid),
.rready_i(rx_fifo_rready),
.rdata_o (rx_fifo_rdata),
.full_o (),
.depth_o(),
.err_o ()
);
assign uart_irq_o = !rx_fifo_empty;
// Synchronize RX and derive rx_start signal
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rx_q <= '0;
end else begin
rx_q <= {rx_q[1:0], uart_rx_i};
end
end
assign rx_start = !rx_q[1] & rx_q[2] & (rx_state_q == IDLE);
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rx_baud_counter_q <= '0;
end else begin
rx_baud_counter_q <= rx_baud_counter_d;
end
end
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rx_state_q <= IDLE;
rx_bit_counter_q <= '0;
rx_current_byte_q <= '0;
// Transition the rx state on both rx_start and an rx_baud_tick
end else if (rx_start || rx_baud_tick) begin
rx_state_q <= rx_state_d;
rx_bit_counter_q <= rx_bit_counter_d;
rx_current_byte_q <= rx_current_byte_d;
end
end
always_comb begin
rx_valid = 0;
rx_bit_counter_d = rx_bit_counter_q;
rx_current_byte_d = rx_current_byte_q;
rx_state_d = rx_state_q;
case (rx_state_q)
IDLE: begin
if (rx_start) begin
rx_state_d = START;
end
end
START: begin
rx_current_byte_d = '0;
rx_bit_counter_d = '0;
if (!rx_q[2]) begin
rx_state_d = PROC;
end else begin
rx_state_d = IDLE;
end
end
PROC: begin
rx_current_byte_d = {rx_q[2], rx_current_byte_q[7:1]};
if (rx_bit_counter_q == 3'd7) begin
rx_state_d = STOP;
end else begin
rx_bit_counter_d = rx_bit_counter_q + 3'd1;
end
end
STOP: begin
if (rx_q[2]) begin
rx_valid = 1;
end
rx_state_d = IDLE;
end
endcase
end
assign write_req = (device_req_i & device_be_i[0] & device_we_i);
assign tx_fifo_wvalid = (reg_addr == UART_TX_REG) & write_req;
assign tx_fifo_rready = tx_baud_tick & tx_next_byte;
assign tx_baud_counter_d = tx_baud_tick ? '0 : tx_baud_counter_q + 1'b1;
assign tx_baud_tick = tx_baud_counter_q == $bits(tx_baud_counter_q)'(ClocksPerBaud - 1);
prim_fifo_sync #(
.Width(8),
.Pass (1'b0),
.Depth(TxFifoDepth)
) u_tx_fifo (
.clk_i,
.rst_ni,
.clr_i (1'b0),
.wvalid_i(tx_fifo_wvalid),
.wready_o(),
.wdata_i (device_wdata_i[7:0]),
.rvalid_o(tx_fifo_rvalid),
.rready_i(tx_fifo_rready),
.rdata_o (tx_fifo_rdata),
.full_o (tx_fifo_full),
.depth_o(),
.err_o ()
);
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
tx_baud_counter_q <= '0;
end else begin
tx_baud_counter_q <= tx_baud_counter_d;
end
end
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
tx_state_q <= IDLE;
tx_bit_counter_q <= '0;
tx_current_byte_q <= '0;
end else if (tx_baud_tick) begin
tx_state_q <= tx_state_d;
tx_bit_counter_q <= tx_bit_counter_d;
tx_current_byte_q <= tx_current_byte_d;
end
end
always_comb begin
uart_tx_o = 1'b0;
tx_bit_counter_d = tx_bit_counter_q;
tx_current_byte_d = tx_current_byte_q;
tx_next_byte = 1'b0;
tx_state_d = tx_state_q;
case (tx_state_q)
IDLE: begin
uart_tx_o = 1'b1;
if (tx_fifo_rvalid) begin
tx_state_d = START;
end
end
START: begin
uart_tx_o = 1'b0;
tx_state_d = PROC;
tx_bit_counter_d = 3'd0;
tx_current_byte_d = tx_fifo_rdata;
tx_next_byte = 1'b1;
end
PROC: begin
uart_tx_o = tx_current_byte_q[0];
tx_current_byte_d = {1'b0, tx_current_byte_q[7:1]};
if (tx_bit_counter_q == 3'd7) begin
tx_state_d = STOP;
end else begin
tx_bit_counter_d = tx_bit_counter_q + 3'd1;
end
end
STOP: begin
uart_tx_o = 1'b1;
if (tx_fifo_rvalid) begin
tx_state_d = START;
end else begin
tx_state_d = IDLE;
end
end
endcase
end
endmodule
extended_ibex/ibex_demo_system/rv_timer.core
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CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:rv_timer"
description: "RISC-V timer"
filesets:
files_rtl_timer:
depend:
- lowrisc:prim:assert
files:
- vendor/lowrisc_ibex/shared/rtl/timer.sv
file_type: systemVerilogSource
targets:
default:
filesets:
- files_rtl_timer
extended_ibex/ibex_demo_system/sw/c/.clang-format
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# Documentation for this configuration is here:
# https://releases.llvm.org/6.0.0/tools/clang/docs/ClangFormatStyleOptions.html
BasedOnStyle: Google
ColumnLimit: 120
AlignConsecutiveAssignments: true
AlignEscapedNewlines: Right
AlignTrailingComments: true
AlignOperands: true
AllowShortBlocksOnASingleLine : false
BinPackArguments: true
BinPackParameters : true
extended_ibex/ibex_demo_system/sw/c/CMakeLists.txt
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cmake_minimum_required(VERSION 3.12)
if(NOT DEFINED CMAKE_TOOLCHAIN_FILE)
set(CMAKE_TOOLCHAIN_FILE "${CMAKE_CURRENT_SOURCE_DIR}/gcc_toolchain.cmake")
endif()
project(demo_system_sw LANGUAGES C ASM)
if(CMAKE_BUILD_TYPE STREQUAL "")
get_property(helpstring CACHE CMAKE_BUILD_TYPE PROPERTY HELPSTRING)
set(CMAKE_BUILD_TYPE "Debug" CACHE STRING "${helpstring}" FORCE)
endif()
option(SIM_CTRL_OUTPUT
"Send string output to simulator control rather than UART")
if(SIM_CTRL_OUTPUT)
add_compile_definitions(SIM_CTRL_OUTPUT)
endif()
add_subdirectory(common)
add_subdirectory(demo)
add_subdirectory(blank)
extended_ibex/ibex_demo_system/sw/c/blank/CMakeLists.txt
+7
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add_executable(blank blank.S)
add_custom_command(
TARGET blank POST_BUILD
COMMAND ${CMAKE_OBJCOPY} -O binary "$<TARGET_FILE:blank>" "$<TARGET_FILE:blank>.bin"
COMMAND srec_cat "$<TARGET_FILE:blank>.bin" -binary -offset 0x0000 -byte-swap 4 -o "$<TARGET_FILE:blank>.vmem" -vmem
VERBATIM)
extended_ibex/ibex_demo_system/sw/c/blank/blank.S
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# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
.section .text
blank_loop:
wfi
j blank_loop
/* =================================================== [ exceptions ] === */
/* This section has to be down here, since we have to disable rvc for it */
.section .vectors, "ax"
.option norvc;
// All unimplemented interrupts/exceptions go to the default_exc_handler.
.org 0x00
.rept 32
jal x0, blank_loop
.endr
// reset vector
.org 0x80
jal x0, blank_loop
extended_ibex/ibex_demo_system/sw/c/common/CMakeLists.txt
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add_library(common OBJECT demo_system.c uart.c timer.c gpio.c pwm.c spi.c crt0.S)
target_include_directories(common INTERFACE "${CMAKE_CURRENT_SOURCE_DIR}")
extended_ibex/ibex_demo_system/sw/c/common/crt0.S
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# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
#include "demo_system_regs.h"
.section .text
default_exc_handler:
jal x0, simple_exc_handler
reset_handler:
/* set all registers to zero */
mv x1, x0
mv x2, x1
mv x3, x1
mv x4, x1
mv x5, x1
mv x6, x1
mv x7, x1
mv x8, x1
mv x9, x1
mv x10, x1
mv x11, x1
mv x12, x1
mv x13, x1
mv x14, x1
mv x15, x1
mv x16, x1
mv x17, x1
mv x18, x1
mv x19, x1
mv x20, x1
mv x21, x1
mv x22, x1
mv x23, x1
mv x24, x1
mv x25, x1
mv x26, x1
mv x27, x1
mv x28, x1
mv x29, x1
mv x30, x1
mv x31, x1
/* stack initilization */
la x2, _stack_start
_start:
.global _start
/* clear BSS */
la x26, _bss_start
la x27, _bss_end
bge x26, x27, zero_loop_end
zero_loop:
sw x0, 0(x26)
addi x26, x26, 4
ble x26, x27, zero_loop
zero_loop_end:
main_entry:
/* jump to main program entry point (argc = argv = 0) */
addi x10, x0, 0
addi x11, x0, 0
jal x1, main
/* Halt simulation */
li x5, SIM_CTRL_BASE + SIM_CTRL_CTRL
li x6, 1
sw x6, 0(x5)
/* If execution ends up here just put the core to sleep */
sleep_loop:
wfi
j sleep_loop
/* =================================================== [ exceptions ] === */
/* This section has to be down here, since we have to disable rvc for it */
.section .vectors, "ax"
.option norvc;
// All unimplemented interrupts/exceptions go to the default_exc_handler.
.org 0x00
.rept 32
jal x0, default_exc_handler
.endr
// reset vector
.org 0x80
jal x0, reset_handler
extended_ibex/ibex_demo_system/sw/c/common/demo_system.c
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#include "demo_system.h"
#include "dev_access.h"
#include "uart.h"
int putchar(int c) {
#ifdef SIM_CTRL_OUTPUT
DEV_WRITE(SIM_CTRL_BASE + SIM_CTRL_OUT, c);
#else
if (c == '\n') {
uart_out(DEFAULT_UART, '\r');
}
uart_out(DEFAULT_UART, c);
#endif
return c;
}
int getchar(void) { return uart_in(DEFAULT_UART); }
int puts(const char* str) {
while (*str) {
putchar(*str++);
}
return 0;
}
void puthex(uint32_t h) {
int cur_digit;
// Iterate through h taking top 4 bits each time and outputting ASCII of hex
// digit for those 4 bits
for (int i = 0; i < 8; i++) {
cur_digit = h >> 28;
if (cur_digit < 10)
putchar('0' + cur_digit);
else
putchar('A' - 10 + cur_digit);
h <<= 4;
}
}
void sim_halt() { DEV_WRITE(SIM_CTRL_BASE + SIM_CTRL_CTRL, 1); }
unsigned int get_mepc() {
uint32_t result;
__asm__ volatile("csrr %0, mepc;" : "=r"(result));
return result;
}
unsigned int get_mcause() {
uint32_t result;
__asm__ volatile("csrr %0, mcause;" : "=r"(result));
return result;
}
unsigned int get_mtval() {
uint32_t result;
__asm__ volatile("csrr %0, mtval;" : "=r"(result));
return result;
}
uint32_t get_mcycle(void) {
uint32_t result;
__asm__ volatile("csrr %0, mcycle;" : "=r"(result));
return result;
}
void reset_mcycle(void) { __asm__ volatile("csrw mcycle, x0"); }
extern uint32_t _vectors_start;
volatile uint32_t* exc_vectors = &_vectors_start;
int install_exception_handler(uint32_t vector_num, void (*handler_fn)(void)) {
if (vector_num >= 32) return 1;
volatile uint32_t* handler_jmp_loc = exc_vectors + vector_num;
int32_t offset = (uint32_t)handler_fn - (uint32_t)handler_jmp_loc;
if ((offset >= (1 << 19)) || (offset < -(1 << 19))) {
return 2;
}
uint32_t offset_uimm = offset;
uint32_t jmp_ins = ((offset_uimm & 0x7fe) << 20) | // imm[10:1] -> 21
((offset_uimm & 0x800) << 9) | // imm[11] -> 20
(offset_uimm & 0xff000) | // imm[19:12] -> 12
((offset_uimm & 0x100000) << 11) | // imm[20] -> 31
0x6f; // J opcode
*handler_jmp_loc = jmp_ins;
__asm__ volatile("fence.i;");
return 0;
}
void enable_interrupts(uint32_t enable_mask) { asm volatile("csrs mie, %0\n" : : "r"(enable_mask)); }
void disable_interrupts(uint32_t disable_mask) { asm volatile("csrc mie, %0\n" : : "r"(disable_mask)); }
void set_global_interrupt_enable(uint32_t enable) {
if (enable) {
asm volatile("csrs mstatus, %0\n" : : "r"(1 << 3));
} else {
asm volatile("csrc mstatus, %0\n" : : "r"(1 << 3));
}
}
void simple_exc_handler(void) {
puts("EXCEPTION!!!\n");
puts("============\n");
puts("MEPC: 0x");
puthex(get_mepc());
puts("\nMCAUSE: 0x");
puthex(get_mcause());
puts("\nMTVAL: 0x");
puthex(get_mtval());
putchar('\n');
while (1)
;
}
extended_ibex/ibex_demo_system/sw/c/common/demo_system.h
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#ifndef DEMO_SYSTEM_H_
#define DEMO_SYSTEM_H_
#include <stdint.h>
#include "demo_system_regs.h"
#include "gpio.h"
#include "uart.h"
#define UART_IRQ_NUM 16
#define UART_IRQ (1 << UART_IRQ_NUM)
#define DEFAULT_UART UART_FROM_BASE_ADDR(UART0_BASE)
#define GPIO_OUT GPIO_FROM_BASE_ADDR(GPIO_BASE + GPIO_OUT_REG)
#define GPIO_IN GPIO_FROM_BASE_ADDR(GPIO_BASE + GPIO_IN_REG)
#define GPIO_IN_DBNC GPIO_FROM_BASE_ADDR(GPIO_BASE + GPIO_IN_DBNC_REG)
#define GPIO_OUT_SHIFT GPIO_FROM_BASE_ADDR(GPIO_BASE + GPIO_OUT_SHIFT_REG)
#define TIMER_IRQ (1 << 7)
#define NUM_PWM_MODULES 12
#define DEFAULT_SPI SPI_FROM_BASE_ADDR(SPI0_BASE)
/**
* Writes character to default UART. Signature matches c stdlib function
* of the same name.
*
* @param c Character to output
* @returns Character output (never fails so no EOF ever returned)
*/
int putchar(int c);
/**
* Reads character from default UART. Signature matches c stdlib function
* of the same name.
*
* @returns Character from the uart rx fifo
*/
int getchar(void);
/**
* Immediately halts the simulation
*/
void sim_halt();
/**
* Writes string to default UART. Signature matches c stdlib function of
* the same name.
*
* @param str String to output
* @returns 0 always (never fails so no error)
*/
int puts(const char *str);
/**
* Writes ASCII hex representation of number to default UART.
*
* @param h Number to output in hex
*/
void puthex(uint32_t h);
/**
* Install an exception handler by writing a `j` instruction to the handler in
* at the appropriate address given the `vector_num`.
*
* @param vector_num Which IRQ the handler is for, must be less than 32. All
* non-interrupt exceptions are handled at vector 0.
*
* @param handle_fn Function pointer to the handler function. The function is
* responsible for interrupt prolog and epilog, such as saving and restoring
* register to the stack and executing `mret` at the end.
*
* @return 0 on success, 1 if `vector_num` out of range, 2 if the address of
* `handler_fn` is too far from the exception handler base to use with a `j`
* instruction.
*/
int install_exception_handler(uint32_t vector_num, void (*handler_fn)(void));
/**
* Set per-interrupt enables (`mie` CSR)
*
* @param enable_mask Any set bit is set in `mie`, enabling the interrupt. Bits
* not set in `enable_mask` aren't changed.
*/
void enable_interrupts(uint32_t enable_mask);
/**
* Clear per-interrupt enables (`mie` CSR)
*
* @param enable_mask Any set bit is cleared in `mie`, disabling the interrupt.
* Bits not set in `enable_mask` aren't changed.
*/
void disable_interrupts(uint32_t disable_mask);
/**
* Set the global interrupt enable (the `mie` field of `mstatus`). This enables
* or disable all interrupts at once.
*
* @param enable Enable interrupts if set, otherwise disabled
*/
void set_global_interrupt_enable(uint32_t enable);
unsigned int get_mepc();
unsigned int get_mcause();
unsigned int get_mtval();
uint32_t get_mcycle(void);
void reset_mcycle(void);
#endif
extended_ibex/ibex_demo_system/sw/c/common/demo_system_regs.h
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#ifndef DEMO_SYSTEM_REGS_H__
#define DEMO_SYSTEM_REGS_H__
#define UART0_BASE 0x80001000
#define GPIO_BASE 0x80000000
#define TIMER_BASE 0x80002000
#define PWM_BASE 0x80003000
#define SPI0_BASE 0x80004000
#define SIM_CTRL_BASE 0x20000
#define SIM_CTRL_OUT 0x0
#define SIM_CTRL_CTRL 0x8
#endif
extended_ibex/ibex_demo_system/sw/c/common/dev_access.h
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#ifndef DEV_ACCESS_H_
#define DEV_ACCESS_H_
#include <stdint.h>
#define DEV_WRITE(addr, val) (*((volatile uint32_t *)(addr)) = val)
#define DEV_READ(addr) (*((volatile uint32_t *)(addr)))
#endif // DEV_ACCESS_H_
extended_ibex/ibex_demo_system/sw/c/common/gpio.c
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#include "gpio.h"
#include "demo_system.h"
#include "dev_access.h"
void set_outputs(gpio_t gpio, uint32_t outputs) { DEV_WRITE(gpio, outputs); }
uint32_t read_gpio(gpio_t gpio) { return DEV_READ(gpio); }
void set_output_bit(gpio_t gpio, uint32_t output_bit_index, uint32_t output_bit) {
output_bit &= 1;
uint32_t output_bits = read_gpio(gpio);
output_bits &= ~(1 << output_bit_index);
output_bits |= (output_bit << output_bit_index);
set_outputs(gpio, output_bits);
}
uint32_t get_output_bit(gpio_t gpio, uint32_t output_bit_index) {
uint32_t output_bits = read_gpio(gpio);
output_bits >>= output_bit_index;
output_bits &= 1;
return output_bits;
}
extended_ibex/ibex_demo_system/sw/c/common/gpio.h
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#ifndef GPIO_H__
#define GPIO_H__
#include <stdint.h>
#define GPIO_OUT_REG 0x0
#define GPIO_IN_REG 0x4
#define GPIO_IN_DBNC_REG 0x8
#define GPIO_OUT_SHIFT_REG 0xC
#define GPIO_OUT_MASK 0xF // Support 4-bit output
typedef void* gpio_t;
#define GPIO_FROM_BASE_ADDR(addr) ((gpio_t)addr)
void set_outputs(gpio_t gpio, uint32_t outputs);
uint32_t read_gpio(gpio_t gpio);
void set_output_bit(gpio_t gpio, uint32_t output_bit_index, uint32_t output_bit);
uint32_t get_output_bit(gpio_t gpio, uint32_t output_bit_index);
#endif
extended_ibex/ibex_demo_system/sw/c/common/pwm.c
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#include "pwm.h"
#include "dev_access.h"
void set_pwm(pwm_t pwm, uint32_t counter, uint32_t pulse_width) {
DEV_WRITE(&pwm[1], counter);
DEV_WRITE(&pwm[0], pulse_width);
}
extended_ibex/ibex_demo_system/sw/c/common/pwm.h
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#ifndef PWM_H__
#define PWM_H__
#include <stdint.h>
typedef uint32_t* pwm_t;
#define PWM_FROM_ADDR_AND_INDEX(addr, index) (&(((pwm_t)addr)[2 * index]))
void set_pwm(pwm_t pwm, uint32_t counter, uint32_t pulse_width);
#endif
extended_ibex/ibex_demo_system/sw/c/common/spi.c
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#include "spi.h"
#include <stdint.h>
#include "dev_access.h"
void spi_init(spi_t *spi, spi_reg_t spi_reg, uint32_t speed) {
spi->reg = spi_reg;
spi->speed = speed;
}
void spi_send_byte_blocking(spi_t *spi, char c) {
while (DEV_READ(spi->reg + SPI_STATUS_REG) & SPI_STATUS_TX_FULL)
;
DEV_WRITE(spi->reg + SPI_TX_REG, c);
}
spi_status_t spi_get_status(spi_t *spi) { return (spi_status_t)DEV_READ(spi->reg + SPI_STATUS_REG); }
extended_ibex/ibex_demo_system/sw/c/common/spi.h
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#ifndef SPI_H__
#define SPI_H__
#include "stdint.h"
#define SPI_TX_REG 0
#define SPI_STATUS_REG 4
#define SPI_STATUS_TX_FULL 1 << 0
#define SPI_STATUS_TX_EMPTY 1 << 1
#define SPI_FROM_BASE_ADDR(addr) ((spi_reg_t)(addr))
typedef void *spi_reg_t;
typedef enum {
spi_status_fifo_full = SPI_STATUS_TX_FULL,
spi_status_fifo_empty = SPI_STATUS_TX_EMPTY,
} spi_status_t;
typedef struct spi {
spi_reg_t reg;
uint32_t speed;
} spi_t;
void spi_init(spi_t *spi, spi_reg_t reg, uint32_t speed);
void spi_send_byte_blocking(spi_t *spi, char c);
spi_status_t spi_get_status(spi_t *spi);
#endif // SPI_H__
extended_ibex/ibex_demo_system/sw/c/common/timer.c
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#include "timer.h"
#include "demo_system.h"
#include "dev_access.h"
volatile uint64_t time_elapsed;
uint64_t time_increment;
void timecmp_update(uint64_t new_time) {
DEV_WRITE(TIMER_BASE + TIMER_MTIMECMP_REG, -1);
DEV_WRITE(TIMER_BASE + TIMER_MTIMECMPH_REG, new_time >> 32);
DEV_WRITE(TIMER_BASE + TIMER_MTIMECMP_REG, new_time);
}
inline static void increment_timecmp(uint64_t time_base) {
uint64_t current_time = timer_read();
current_time += time_base;
timecmp_update(current_time);
}
void simple_timer_handler(void) __attribute__((interrupt));
void simple_timer_handler(void) {
increment_timecmp(time_increment);
time_elapsed++;
}
void timer_init(void) { install_exception_handler(7, &simple_timer_handler); }
uint64_t timer_read() {
uint32_t current_timeh;
uint32_t current_time;
// check if time overflowed while reading and try again
do {
current_timeh = DEV_READ(TIMER_BASE + TIMER_MTIMEH_REG);
current_time = DEV_READ(TIMER_BASE + TIMER_MTIME_REG);
} while (current_timeh != DEV_READ(TIMER_BASE + TIMER_MTIMEH_REG));
uint64_t final_time = ((uint64_t)current_timeh << 32) | current_time;
return final_time;
}
uint64_t get_elapsed_time(void) { return time_elapsed; }
void timer_enable(uint64_t time_base) {
time_elapsed = 0;
time_increment = time_base;
// Set timer values
increment_timecmp(time_base);
enable_interrupts(TIMER_IRQ);
set_global_interrupt_enable(1);
}
void timer_disable(void) { asm volatile("csrc mie, %0\n" : : "r"(0x80)); }
extended_ibex/ibex_demo_system/sw/c/common/timer.h
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#ifndef TIMER_H__
#define TIMER_H__
#include "stdint.h"
#define TIMER_MTIME_REG 0x0
#define TIMER_MTIMEH_REG 0x4
#define TIMER_MTIMECMP_REG 0x8
#define TIMER_MTIMECMPH_REG 0xC
void timer_init();
uint64_t timer_read();
uint64_t get_elapsed_time();
void timer_enable(uint64_t time_base);
void timer_disable();
#endif // TIMER_H__
extended_ibex/ibex_demo_system/sw/c/common/uart.c
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#include "uart.h"
#include "demo_system.h"
#include "dev_access.h"
void uart_enable_rx_int(void) {
enable_interrupts(UART_IRQ);
set_global_interrupt_enable(1);
}
int uart_in(uart_t uart) {
int res = UART_EOF;
if (!(DEV_READ(uart + UART_STATUS_REG) & UART_STATUS_RX_EMPTY)) {
res = DEV_READ(uart + UART_RX_REG);
}
return res;
}
void uart_out(uart_t uart, char c) {
while (DEV_READ(uart + UART_STATUS_REG) & UART_STATUS_TX_FULL)
;
DEV_WRITE(uart + UART_TX_REG, c);
}
extended_ibex/ibex_demo_system/sw/c/common/uart.h
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#ifndef UART_H__
#define UART_H__
#define UART_RX_REG 0
#define UART_TX_REG 4
#define UART_STATUS_REG 8
#define UART_STATUS_RX_EMPTY 1
#define UART_STATUS_TX_FULL 2
#define UART_EOF -1
typedef void* uart_t;
#define UART_FROM_BASE_ADDR(addr) ((uart_t)(addr))
void uart_enable_rx_int(void);
int uart_in(uart_t uart);
void uart_out(uart_t uart, char c);
#endif // UART_H__
extended_ibex/ibex_demo_system/sw/c/demo/CMakeLists.txt
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add_subdirectory(hello_world)
add_subdirectory(lcd_st7735)
add_subdirectory(simpleserial-aes)
add_subdirectory(basic-passwdcheck)
extended_ibex/ibex_demo_system/sw/c/demo/basic-passwdcheck/CMakeLists.txt
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add_definitions(-DSS_VER=1 -DHAL_TYPE=HAL_ibex)
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../../../../vendor/newae/crypto)
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../../../../vendor/newae/hal)
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../../../../vendor/newae/simpleserial)
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../../common)
add_executable(basic-passwdcheck ${CMAKE_CURRENT_SOURCE_DIR}/../../../../vendor/newae/basic-passwdcheck/basic-passwdcheck.c)
target_link_libraries(basic-passwdcheck common simpleserial)
extended_ibex/ibex_demo_system/sw/c/demo/basic-passwdcheck/README
+23
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ChipWhisperer basic-passwdcheck application, intended to be run on a
ChipWhisperer FPGA target (synth_cw305 or synth_cw312a35 targets).
This can then be used with NewAE's "Power Analysis for Password Bypass"
notebook
(https://github.com/newaetech/chipwhisperer-jupyter/tree/master/courses/sca101/),
with modifications to the target clock and baud rate:
scope.clock.adc_mul = 1 # if using CW-Husky
scope.clock.adc_src = 'clkgen_x1' # if using CW-lite/pro
scope.clock.clkgen_freq = 100e6
target.baud = 115200
Note that the password bypass attack will not work well on the CW305 target
since that target lacks a method to reset the Ibex processor from the host PC
(top_cw305.sv could be modified to achieve this). However it will work on the
CW312-A35 target.
Note that this application (and many others!) can also be built in the
ChipWhisperer repository:
https://github.com/newaetech/chipwhisperer/tree/develop/hardware/victims/firmware/basic-passwdcheck/
using:
make PLATFORM=CW305_IBEX CRYPTO_TARGET=NONE
extended_ibex/ibex_demo_system/sw/c/demo/hello_world/CMakeLists.txt
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add_executable(demo main.c)
target_link_libraries(demo common)
extended_ibex/ibex_demo_system/sw/c/demo/hello_world/main.c
+101
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#include <stdbool.h>
#include "demo_system.h"
#include "gpio.h"
#include "pwm.h"
#include "timer.h"
#define USE_GPIO_SHIFT_REG 0
void test_uart_irq_handler(void) __attribute__((interrupt));
void test_uart_irq_handler(void) {
int uart_in_char;
while ((uart_in_char = uart_in(DEFAULT_UART)) != -1) {
uart_out(DEFAULT_UART, uart_in_char);
uart_out(DEFAULT_UART, '\r');
uart_out(DEFAULT_UART, '\n');
}
}
int main(void) {
install_exception_handler(UART_IRQ_NUM, &test_uart_irq_handler);
uart_enable_rx_int();
// This indicates how often the timer gets updated.
timer_init();
timer_enable(5000000);
uint64_t last_elapsed_time = get_elapsed_time();
// Reset green LEDs to off
set_outputs(GPIO_OUT, 0x0);
// PWM variables
uint32_t counter = UINT8_MAX;
uint32_t brightness = 0;
bool ascending = true;
// The three least significant bits correspond to RGB, where B is the leas significant.
uint8_t color = 7;
while (1) {
uint64_t cur_time = get_elapsed_time();
if (cur_time != last_elapsed_time) {
last_elapsed_time = cur_time;
// Disable interrupts whilst outputting to prevent output for RX IRQ
// happening in the middle
set_global_interrupt_enable(0);
// Print this to UART (use the screen command to see it).
puts("Hello World! ");
puthex(last_elapsed_time);
puts(" Input Value: ");
uint32_t in_val = read_gpio(GPIO_IN_DBNC);
puthex(in_val);
putchar('\n');
// Re-enable interrupts with output complete
set_global_interrupt_enable(1);
// Cycling through green LEDs when BTN0 is pressed
if (USE_GPIO_SHIFT_REG) {
set_outputs(GPIO_OUT_SHIFT, in_val);
} else {
uint32_t out_val = read_gpio(GPIO_OUT);
out_val = ((out_val << 1) & GPIO_OUT_MASK) | (in_val & 0x1);
set_outputs(GPIO_OUT, out_val);
}
// Going from bright to dim on PWM
for (int i = 0; i < NUM_PWM_MODULES; i++) {
set_pwm(PWM_FROM_ADDR_AND_INDEX(PWM_BASE, i), ((1 << (i % 3)) & color) ? counter : 0,
brightness ? 1 << (brightness - 1) : 0);
}
if (ascending) {
brightness++;
if (brightness >= 5) {
ascending = false;
}
} else {
brightness--;
// When LEDs are off cycle through the colors
if (brightness == 0) {
ascending = true;
color++;
if (color >= 8) {
color = 1;
}
}
}
}
asm volatile("wfi");
}
}
extended_ibex/ibex_demo_system/sw/c/demo/lcd_st7735/CMakeLists.txt
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add_library(lcd_st7735_lib
${CMAKE_CURRENT_SOURCE_DIR}/../../../../vendor/display_drivers/core/lcd_base.c
${CMAKE_CURRENT_SOURCE_DIR}/../../../../vendor/display_drivers/core/lucida_console_10pt.c
${CMAKE_CURRENT_SOURCE_DIR}/../../../../vendor/display_drivers/core/lucida_console_12pt.c
${CMAKE_CURRENT_SOURCE_DIR}/../../../../vendor/display_drivers/st7735/lcd_st7735.c
)
# add_executable(lcd_st7735 main.c)
add_executable(lcd_st7735 main.c lcd.c fractal_fixed.c fractal_float.c fractal_palette.c)
# pull in core dependencies and additional i2c hardware support
target_link_libraries(lcd_st7735 common lcd_st7735_lib)
target_include_directories(lcd_st7735 PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/../../../../vendor/display_drivers)
extended_ibex/ibex_demo_system/sw/c/demo/lcd_st7735/fractal.h
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#ifndef LCD_ST_7735_FRACTAL
#define LCD_ST_7735_FRACTAL
#include "lcd.h"
void fractal_mandelbrot_float(St7735Context *lcd);
void fractal_mandelbrot_fixed(St7735Context *lcd);
extern uint16_t rgb_iters_palette[51];
#endif
extended_ibex/ibex_demo_system/sw/c/demo/lcd_st7735/fractal_fixed.c
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#include <stdint.h>
#include "fractal.h"
#include "lcd.h"
#define FP_EXP 12
#define FP_MANT 15
#define MAKE_FP(i, f, f_bits) ((i << FP_EXP) | (f << (FP_EXP - f_bits)))
typedef uint32_t cmplx_fixed_packed_t;
typedef struct {
int32_t real;
int32_t imag;
} cmplx_fixed_t;
int32_t fp_clamp(int32_t x) {
if ((x < 0) && (x < -(1 << FP_MANT))) {
return -(1 << FP_MANT);
}
if ((x > 0) && (x >= (1 << FP_MANT))) {
return (1 << FP_MANT) - 1;
}
return x;
}
int32_t to_fp(int32_t x) {
int32_t res;
res = fp_clamp(x << FP_EXP);
return res;
}
int32_t fp_add(int32_t a, int32_t b) { return fp_clamp(a + b); }
int32_t fp_mul(int32_t a, int32_t b) { return fp_clamp((a * b) >> FP_EXP); }
int32_t cmplx_fixed_abs_sq(cmplx_fixed_t c) { return fp_mul(c.real, c.real) + fp_mul(c.imag, c.imag); }
cmplx_fixed_t cmplx_fixed_mul(cmplx_fixed_t c1, cmplx_fixed_t c2) {
cmplx_fixed_t res;
res.real = fp_add(fp_mul(c1.real, c2.real), -fp_mul(c1.imag, c2.imag));
res.imag = fp_add(fp_mul(c1.real, c2.imag), fp_mul(c1.imag, c2.real));
return res;
}
cmplx_fixed_t cmplx_fixed_add(cmplx_fixed_t c1, cmplx_fixed_t c2) {
cmplx_fixed_t res;
res.real = fp_add(c1.real, c2.real);
res.imag = fp_add(c1.imag, c2.imag);
return res;
}
int mandel_iters_fixed(cmplx_fixed_t c, uint32_t max_iters) {
cmplx_fixed_t iter_val;
iter_val = c;
for (uint32_t i = 0; i < max_iters; ++i) {
iter_val = cmplx_fixed_add(cmplx_fixed_mul(iter_val, iter_val), c);
if (cmplx_fixed_abs_sq(iter_val) > MAKE_FP(4, 0, 0)) {
return i;
}
}
return max_iters;
}
void fractal_mandelbrot_fixed(St7735Context *lcd) {
cmplx_fixed_t cur_p;
int32_t inc;
LCD_rectangle rectangle = {.origin = {.x = 0, .y = 0}, .width = 160, .height = 128};
lcd_st7735_clean(lcd);
lcd_st7735_rgb565_start(lcd, rectangle);
cur_p.real = -MAKE_FP(1, 0x3, 2);
cur_p.imag = MAKE_FP(1, 0, 0);
inc = MAKE_FP(0, 0x40, 12);
for (int y = 0; y < 128; ++y) {
for (int x = 0; x < 160; ++x) {
int iters = mandel_iters_fixed(cur_p, 50);
uint16_t rgb = rgb_iters_palette[iters];
lcd_st7735_rgb565_put(lcd, (uint8_t *)&rgb, sizeof(rgb));
cur_p.real += inc;
}
cur_p.imag -= inc;
cur_p.real = -MAKE_FP(1, 0x3, 2);
}
lcd_st7735_rgb565_finish(lcd);
}
extended_ibex/ibex_demo_system/sw/c/demo/lcd_st7735/fractal_float.c
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#include <stdint.h>
#include "fractal.h"
#include "lcd.h"
typedef struct {
float real;
float imag;
} cmplx_float_t;
float cmplx_float_abs_sq(cmplx_float_t c) { return c.real * c.real + c.imag * c.imag; }
cmplx_float_t cmplx_float_mul(cmplx_float_t c1, cmplx_float_t c2) {
cmplx_float_t res;
res.real = c1.real * c2.real - c1.imag * c2.imag;
res.imag = c1.real * c2.imag + c1.imag * c2.real;
return res;
}
cmplx_float_t cmplx_float_add(cmplx_float_t c1, cmplx_float_t c2) {
cmplx_float_t res;
res.real = c1.real + c2.real;
res.imag = c1.imag + c2.imag;
return res;
}
int mandel_iters_float(cmplx_float_t c, uint32_t max_iters) {
cmplx_float_t iter_val;
iter_val = c;
for (uint32_t i = 0; i < max_iters; ++i) {
iter_val = cmplx_float_add(cmplx_float_mul(iter_val, iter_val), c);
if (cmplx_float_abs_sq(iter_val) > 4.0f) {
return i;
}
}
return max_iters;
}
void fractal_mandelbrot_float(St7735Context *lcd) {
cmplx_float_t cur_p;
float real_inc;
float imag_inc;
LCD_rectangle rectangle = {.origin = {.x = 0, .y = 0}, .width = 160, .height = 128};
lcd_st7735_clean(lcd);
lcd_st7735_rgb565_start(lcd, rectangle);
cur_p.real = -1.75f;
cur_p.imag = 1.0f;
real_inc = 2.5f / 160.0f;
imag_inc = -2.0f / 128.0f;
for (int y = 0; y < 128; ++y) {
for (int x = 0; x < 160; ++x) {
int iters = mandel_iters_float(cur_p, 50);
uint16_t rgb = rgb_iters_palette[iters];
lcd_st7735_rgb565_put(lcd, (uint8_t *)&rgb, sizeof(rgb));
cur_p.real += real_inc;
}
cur_p.imag += imag_inc;
cur_p.real = -1.75f;
}
lcd_st7735_rgb565_finish(lcd);
}
extended_ibex/ibex_demo_system/sw/c/demo/lcd_st7735/fractal_palette.c
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#include <stdint.h>
#include "fractal.h"
uint16_t rgb_iters_palette[51] = {
0x91e7, 0x7ca7, 0x5ca7, 0x44a7, 0x3ca9, 0x3cab, 0x3cad, 0x3caf, 0x3cb1, 0x3cb2, 0x3c52, 0x3bf2, 0x3b92,
0x3b52, 0x3b12, 0x3ab2, 0x3a72, 0x3a32, 0x39f2, 0x41f2, 0x49f2, 0x51f2, 0x59f2, 0x59f2, 0x61f2, 0x69f2,
0x71f2, 0x79f2, 0x79f2, 0x81f2, 0x89f2, 0x91f2, 0x91f2, 0x91f1, 0x91f1, 0x91f0, 0x91ef, 0x91ef, 0x91ee,
0x91ed, 0x91ed, 0x91ec, 0x91eb, 0x91eb, 0x91ea, 0x91ea, 0x91e9, 0x91e9, 0x91e8, 0x91e7, 0x91e7};
extended_ibex/ibex_demo_system/sw/c/demo/lcd_st7735/lcd.c
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#include "lcd.h"
#include "st7735/lcd_st7735.h"
#include "string.h"
void lcd_show_menu(St7735Context *lcd, Menu_t *menu) {
size_t line = 0;
size_t selected = 1;
// Clean the screen.
lcd_st7735_fill_rectangle(
lcd, (LCD_rectangle){.origin = {.x = 0, .y = 0}, .width = lcd->parent.width, .height = lcd->parent.font->height},
menu->color);
// Invert background and foreground colors for the title.
lcd_st7735_set_font_colors(lcd, menu->color, menu->background);
lcd_println(lcd, menu->title, alined_center, line++);
// Set the colors for the menu items.
lcd_st7735_set_font_colors(lcd, menu->background, menu->color);
// Draw the menu items.
for (int i = 0; i < menu->items_count; ++i) {
lcd_println(lcd, menu->items[i], alined_left, line++);
}
// Drow a boarder around the selected item.
selected++;
lcd_st7735_draw_horizontal_line(
lcd, (LCD_Line){{.x = 0, .y = lcd->parent.font->height * selected}, lcd->parent.width}, menu->selected_color);
lcd_st7735_draw_horizontal_line(
lcd, (LCD_Line){{.x = 0, .y = lcd->parent.font->height * (selected + 1) - 1}, lcd->parent.width},
menu->selected_color);
lcd_st7735_draw_vertical_line(
lcd, (LCD_Line){{.x = 0, .y = lcd->parent.font->height * selected}, lcd->parent.font->height - 1},
menu->selected_color);
lcd_st7735_draw_vertical_line(
lcd,
(LCD_Line){{.x = lcd->parent.width - 1, .y = lcd->parent.font->height * selected}, lcd->parent.font->height - 1},
menu->selected_color);
}
void lcd_println(St7735Context *lcd, const char *str, TextAlignment_t alignment, int32_t line) {
// Align the test in the left.
LCD_Point pos = {.y = line * lcd->parent.font->height, .x = 0};
if (alignment != alined_left) {
// Align the text in the right.
pos.x = lcd->parent.width - strlen(str) * lcd->parent.font->descriptor_table->width;
if (alignment == alined_center) {
// Align the test in the center.
pos.x /= 2;
}
}
// Draw the text.
lcd_st7735_puts(lcd, pos, str);
}
extended_ibex/ibex_demo_system/sw/c/demo/lcd_st7735/lcd.h
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#ifndef LCD_ST_7735_LCD
#define LCD_ST_7735_LCD
#include "st7735/lcd_st7735.h"
#include "string.h"
// Color codes in BGR format.
enum {
BGRColorBlack = 0x000000,
BGRColorBlue = 0xFF0000,
BGRColorGreen = 0x00FF00,
BGRColorRed = 0x0000FF,
BGRColorWhite = 0xFFFFFF,
};
// Text alignment.
typedef enum TextAlignment {
alined_right,
alined_center,
alined_left,
} TextAlignment_t;
/**
* @brief Draw a NULL terminated string in the screen.
*
* @param lcd LCD handle.
* @param str NULL terminated string.
* @param alignment Text horizontal alignment in the screen.
* @param line Position line starting at 0. The total number of lines will vary depending on
* the font size.
*/
void lcd_println(St7735Context *lcd, const char *str, TextAlignment_t alignment, int32_t line);
typedef struct Menu {
const char *title; // Pointer to a NULL terminated string to be used as the title.
const char **items; // Pointer to a array of NULL terminated strings with the menus.
size_t items_count; // Size of the items array.
uint32_t color; // Foreground color (text color).
uint32_t background; // Background color.
uint32_t selected_color; // Color of the selection box.
} Menu_t;
/**
* @brief Draw a menu in the screen.
*
* @param lcd LCD handle.
* @param menu Menu configuration.
*/
void lcd_show_menu(St7735Context *lcd, Menu_t *menu);
#endif
extended_ibex/ibex_demo_system/sw/c/demo/lcd_st7735/lowrisc_logo.h
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
static char __attribute__((aligned(4))) lowrisc_logo_105x80[] = {
0x9e, 0xf7, 0xbe, 0xf7, 0xbe, 0xf7, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xbf, 0xff, 0xbe, 0xf7, 0x9e,
0xf7, 0x9e, 0xf7, 0xbe, 0xf7, 0xbf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xbf, 0xff,
0xbe, 0xf7, 0x9e, 0xf7, 0xbf, 0xff, 0xbf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xbf,
0xff, 0xbe, 0xf7, 0xbe, 0xf7, 0xbf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff,
0xdf, 0xff, 0xbf, 0xff, 0xbe, 0xf7, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbf,
0xff, 0x5d, 0xff, 0x9b, 0xfe, 0xf8, 0xfd, 0x36, 0xf5, 0xb4, 0xf4, 0x73, 0xf4, 0x32, 0xf4, 0x53, 0xf4, 0x93, 0xf4,
0x15, 0xf5, 0xb7, 0xfd, 0x7a, 0xfe, 0x1c, 0xff, 0xbe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xdf,
0xff, 0xdf, 0xff, 0xbf, 0xff, 0xbf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x5d, 0xff, 0xf8, 0xfd,
0xd1, 0xeb, 0xad, 0xea, 0x4c, 0xe2, 0x0b, 0xe2, 0xea, 0xe1, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xea,
0xe1, 0xea, 0xe1, 0x0b, 0xe2, 0x2b, 0xe2, 0x8d, 0xea, 0x6f, 0xeb, 0x36, 0xf5, 0xfc, 0xfe, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff,
0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xbf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xbb, 0xfe, 0xb4, 0xf4, 0xee, 0xea, 0xea,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x8c, 0xea, 0x12, 0xf4, 0x39,
0xfe, 0xbe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1c, 0xff, 0x93, 0xf4, 0x8c, 0xea, 0xea, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xea, 0xe1, 0xea, 0xe1, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0x2b, 0xe2, 0xb0, 0xeb, 0x7a, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbf, 0xff, 0xd8, 0xfd, 0xcd, 0xea, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xea, 0xe1, 0x2f, 0xeb, 0xf5, 0xf4, 0x97, 0xfd, 0x36, 0xf5, 0x90, 0xeb, 0x2b,
0xe2, 0xca, 0xe1, 0xca, 0xe1, 0x4c, 0xe2, 0xd4, 0xf4, 0x5d, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0x9e, 0xff, 0x32, 0xf4, 0x0b, 0xe2, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x2b, 0xe2, 0x15, 0xf5, 0x7e, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbf, 0xff,
0xb8, 0xfd, 0x8c, 0xea, 0xca, 0xe1, 0xca, 0xe1, 0xea, 0xe1, 0x70, 0xeb, 0xbb, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0x3d, 0xff, 0x2f, 0xeb, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x53, 0xf4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0x56, 0xf5, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x4c, 0xe2, 0x19, 0xfe, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0x5d, 0xff, 0x0e, 0xeb, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x0b, 0xe2, 0xdc, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0x5d, 0xff, 0xcd, 0xea, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x6c, 0xea, 0xd8,
0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
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0xe1, 0xca, 0xe1, 0xcd, 0xea, 0xbb, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xdf, 0xff, 0x93, 0xf4, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x2b, 0xe2, 0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x9e, 0xff, 0x0e, 0xeb, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xea, 0xe1, 0x4f, 0xeb, 0x5d, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x0b, 0xe2, 0x0e, 0xeb, 0x73, 0xf4, 0xd4, 0xf4, 0x12, 0xf4, 0x8d, 0xea, 0xea,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0x15, 0xf5, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0x0b, 0xe2, 0x36, 0xf5, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xea, 0xe1, 0x6f, 0xeb, 0x9e, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xe2, 0x0b, 0xe2, 0x0b, 0xe2, 0x4f, 0xeb, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xbb, 0xfe, 0x4c, 0xe2, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0x6c, 0xea, 0xff, 0xff, 0xd1, 0xf3, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xea, 0xe1, 0xb7, 0xfd, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xf5, 0xf4, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xcd, 0xea, 0xf5, 0xf4, 0x56, 0xf5, 0x56, 0xf5, 0x56, 0xf5,
0x56, 0xf5, 0x56, 0xf5, 0x56, 0xf5, 0x5a, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xbf, 0xff, 0x0e, 0xeb, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0x6c, 0xea, 0xff, 0xff, 0xd1, 0xf3, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xd1, 0xeb,
0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0x9e, 0xff, 0x2f, 0xeb, 0xca, 0xe1, 0xea, 0xe1, 0xee, 0xea, 0x7a, 0xfe, 0xdf, 0xff, 0x5d, 0xff, 0x5d, 0xff, 0x5d,
0xff, 0x5d, 0xff, 0x5d, 0xff, 0x5d, 0xff, 0x9e, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x4f, 0xeb, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0x6c, 0xea, 0xff, 0xff, 0xd1, 0xf3, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x8c,
0xea, 0x3d, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0x9b, 0xfe, 0x6c, 0xe2, 0xca, 0xe1, 0x0e, 0xeb, 0xdb, 0xfe, 0x7e, 0xff, 0x52, 0xf4, 0xcd, 0xea, 0xad, 0xea,
0xad, 0xea, 0xad, 0xea, 0xad, 0xea, 0xad, 0xea, 0x73, 0xf4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x5d, 0xff, 0xcd, 0xea, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0x6c, 0xea, 0xff, 0xff, 0xd1, 0xf3, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xea, 0xe1, 0x15, 0xf5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0x56, 0xf5, 0x0b, 0xe2, 0x0e, 0xeb, 0x9a, 0xfe, 0x9e, 0xff, 0x53, 0xf4, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xad, 0xea, 0xdc, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0x35, 0xf5, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x6c, 0xea, 0xff, 0xff, 0xd1, 0xf3, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xea, 0xe1, 0xf1, 0xf3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0x5d, 0xff, 0x0e, 0xeb, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xea,
0xe1, 0x4f, 0xeb, 0x3d, 0xff, 0x5d, 0xff, 0x6f, 0xeb, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xea, 0xe1, 0x6f, 0xeb, 0x5d, 0xff, 0x5d, 0xff, 0x90, 0xeb, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x0b, 0xe2, 0x9b, 0xfe,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd4, 0xf4, 0xea, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x6c, 0xea, 0x5a, 0xfe, 0xdf, 0xff, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xfc, 0xfe, 0x4f, 0xeb, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xd1, 0xeb, 0x7e, 0xff, 0xfc, 0xfe, 0x2e, 0xeb, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xd1, 0xeb, 0x5d, 0xff, 0x1c, 0xff, 0x4f, 0xeb, 0xea, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x8d, 0xea, 0x9e,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x39, 0xfe, 0x2b,
0xe2, 0xca, 0xe1, 0xca, 0xe1, 0x6c, 0xe2, 0xd8, 0xfd, 0xdf, 0xff, 0x15, 0xf5, 0xad, 0xea, 0x35, 0xf5, 0x39, 0xfe,
0x19, 0xfe, 0x15, 0xf5, 0xad, 0xea, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xea, 0xe1, 0xb0,
0xeb, 0x3d, 0xff, 0x3d, 0xff, 0x90, 0xeb, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xea, 0xe1, 0x90, 0xeb, 0x3d, 0xff, 0x1c, 0xff, 0x90, 0xeb, 0xea, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xea, 0xe1, 0x52, 0xf4,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x5e, 0xff,
0xee, 0xea, 0xca, 0xe1, 0x6c, 0xea, 0x39, 0xfe, 0xbf, 0xff, 0xf5, 0xf4, 0x2b, 0xe2, 0xca, 0xe1, 0xea, 0xe1, 0x0b,
0xe2, 0x0b, 0xe2, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xd1, 0xeb,
0x7e, 0xff, 0xfc, 0xfe, 0x0e, 0xeb, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xf1, 0xf3, 0x7e, 0xff, 0xfc, 0xfe, 0x2f, 0xeb, 0xea, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x4b, 0xe2, 0xfc,
0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdf,
0xff, 0x53, 0xf4, 0x8c, 0xea, 0xf8, 0xfd, 0xdf, 0xff, 0x15, 0xf5, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xea, 0xe1, 0xd1, 0xeb, 0x3d,
0xff, 0x1c, 0xff, 0x90, 0xeb, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xea, 0xe1, 0xb0, 0xeb, 0x3d, 0xff, 0x1c, 0xff, 0x6f, 0xeb, 0xea, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x6f, 0xeb,
0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xfc, 0xfe, 0x39, 0xfe, 0x9e, 0xff, 0xf5, 0xf4, 0x2b, 0xe2, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xea, 0xe1, 0x12, 0xf4, 0x5e, 0xff,
0xdc, 0xfe, 0x4f, 0xeb, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xf1, 0xeb, 0x7e, 0xff, 0xdb, 0xfe, 0x2f, 0xeb, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xea, 0xe1, 0x36,
0xf5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xf5, 0xf4, 0x0b, 0xe2, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xea, 0xe1, 0xb1, 0xeb, 0x3d, 0xff, 0xfc,
0xfe, 0x6f, 0xeb, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x0b, 0xe2, 0xcd, 0xea, 0xb0, 0xeb, 0x90, 0xeb,
0xad, 0xea, 0x2b, 0xe2, 0xb0, 0xeb, 0x3d, 0xff, 0x3d, 0xff, 0x6f, 0xeb, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xed, 0xea,
0x5d, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7e, 0xff, 0x0e, 0xeb, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x12, 0xf4, 0x7e, 0xff, 0xbb, 0xfe,
0x4f, 0xeb, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xee, 0xea, 0xd8, 0xfd, 0x5d, 0xff, 0xbf, 0xff, 0xbf,
0xff, 0x3d, 0xff, 0x19, 0xfe, 0x9e, 0xff, 0xbb, 0xfe, 0x0e, 0xeb, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x2b, 0xe2, 0xd8,
0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x36, 0xf5, 0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x0b, 0xe2, 0xd0, 0xeb, 0x3d, 0xff, 0x1c, 0xff, 0x4f,
0xeb, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x2b, 0xe2, 0x39, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x90, 0xeb, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xd1, 0xeb,
0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7e, 0xff, 0xb0, 0xeb, 0xca, 0xe1, 0xca, 0xe1, 0xca,
0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0x12, 0xf4, 0x7e, 0xff, 0xbb, 0xfe, 0x2e, 0xeb,
0xea, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xea, 0xe1, 0x73, 0xf4, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x12, 0xf4, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1,
0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xca, 0xe1, 0xad, 0xea, 0xbb,
0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1c, 0xff, 0x0e, 0xeb, 0xca, 0xe1,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x9a, 0xd6, 0x55,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb3, 0x9c,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x72,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x92, 0x94, 0x6a, 0x52, 0x6a,
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0x62, 0xab, 0x5a, 0x8a, 0x5a, 0xb3, 0x9c, 0xdf, 0xff, 0xff, 0xff, 0xdf, 0xff, 0x10, 0x84, 0x8a, 0x5a, 0x8a, 0x52,
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0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x72, 0x94, 0x6a, 0x52,
0x6a, 0x52, 0x8a, 0x5a, 0x96, 0xb5, 0xff, 0xff, 0xff, 0xff, 0x9e, 0xf7, 0x72, 0x94, 0x8a, 0x5a, 0x6a, 0x52, 0x6a,
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0x31, 0x8c, 0x6a, 0x52, 0x6a, 0x52, 0x6a, 0x52, 0x0c, 0x6b, 0x3c, 0xe7, 0xff, 0xff, 0x9e, 0xf7, 0x6e, 0x73, 0x6a,
0x52, 0x6a, 0x52, 0x6a, 0x52, 0x6a, 0x52, 0xcb, 0x5a, 0x8e, 0x73, 0x92, 0x94, 0xf7, 0xbd, 0x3d, 0xef, 0xdf, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdb, 0xde, 0xeb, 0x62, 0x6a, 0x52, 0x6a, 0x52, 0x6a, 0x52, 0x4d, 0x6b, 0x3c,
0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x71, 0x94, 0x6a,
0x52, 0x6a, 0x52, 0x8a, 0x5a, 0xb7, 0xbd, 0xff, 0xff, 0xdf, 0xff, 0xf3, 0xa4, 0x8a, 0x52, 0x6a, 0x52, 0x6a, 0x52,
0x6a, 0x52, 0xab, 0x5a, 0xaa, 0x5a, 0xaa, 0x5a, 0x14, 0xa5, 0x7e, 0xf7, 0xd7, 0xbd, 0x96, 0xb5, 0xff, 0xff, 0x3d,
0xef, 0x4d, 0x6b, 0x6a, 0x52, 0x6a, 0x52, 0xec, 0x62, 0xfc, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xb2, 0x9c, 0x6a, 0x52,
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0x9a, 0xd6, 0x96, 0xb5, 0x2d, 0x6b, 0x6a, 0x52, 0x6a, 0x52, 0x6a, 0x52, 0x0c, 0x63, 0x7d, 0xf7, 0xff, 0xff, 0xff,
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0xa4, 0x5d, 0xef, 0xff, 0xff, 0xff, 0xff, 0x79, 0xce, 0xab, 0x5a, 0x6a, 0x52, 0x6a, 0x52, 0x6a, 0x52, 0x51, 0x8c,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff,
};
extended_ibex/ibex_demo_system/sw/c/demo/lcd_st7735/main.c
+178
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@@ -0,0 +1,178 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#include "core/lucida_console_10pt.h"
#include "demo_system.h"
#include "fractal.h"
#include "gpio.h"
#include "lcd.h"
#include "lowrisc_logo.h"
#include "spi.h"
#include "st7735/lcd_st7735.h"
#include "timer.h"
// Constants.
enum {
// Pin out mapping.
LcdCsPin = 0,
LcdRstPin,
LcdDcPin,
LcdBlPin,
LcdMosiPin,
LcdSclkPin,
// Spi clock rate.
SpiSpeedHz = 5 * 100 * 1000,
};
// Buttons
typedef enum {
BTN0 = 0b0001,
BTN1 = 0b0010,
BTN2 = 0b0100,
BTN3 = 0b1000,
} Buttons_t;
// Local functions declaration.
static uint32_t spi_write(void *handle, uint8_t *data, size_t len);
static uint32_t gpio_write(void *handle, bool cs, bool dc);
static void timer_delay(uint32_t ms);
static void fractal_test(St7735Context *lcd);
static Buttons_t scan_buttons(uint32_t timeout, Buttons_t def);
int main(void) {
timer_init();
// Set the initial state of the LCD control pins.
set_output_bit(GPIO_OUT, LcdDcPin, 0x0);
set_output_bit(GPIO_OUT, LcdBlPin, 0x1);
set_output_bit(GPIO_OUT, LcdCsPin, 0x0);
// Init spi driver.
spi_t spi;
spi_init(&spi, DEFAULT_SPI, SpiSpeedHz);
// Reset LCD.
set_output_bit(GPIO_OUT, LcdRstPin, 0x0);
timer_delay(150);
set_output_bit(GPIO_OUT, LcdRstPin, 0x1);
// Init LCD driver and set the SPI driver.
St7735Context lcd;
LCD_Interface interface = {
.handle = &spi, // SPI handle.
.spi_write = spi_write, // SPI write callback.
.gpio_write = gpio_write, // GPIO write callback.
.timer_delay = timer_delay, // Timer delay callback.
};
lcd_st7735_init(&lcd, &interface);
// Set the LCD orientation.
lcd_st7735_set_orientation(&lcd, LCD_Rotate180);
// Setup text font bitmaps to be used and the colors.
lcd_st7735_set_font(&lcd, &lucidaConsole_10ptFont);
lcd_st7735_set_font_colors(&lcd, BGRColorWhite, BGRColorBlack);
// Clean display with a white rectangle.
lcd_st7735_clean(&lcd);
// Draw the splash screen with a RGB 565 bitmap and text in the bottom.
lcd_st7735_draw_rgb565(&lcd, (LCD_rectangle){.origin = {.x = (160 - 105) / 2, .y = 5}, .width = 105, .height = 80},
(uint8_t *)lowrisc_logo_105x80);
lcd_println(&lcd, "Booting...", alined_center, 7);
timer_delay(1000);
do {
lcd_st7735_clean(&lcd);
// Show the main menu.
const char *items[] = {
"0. Fractal",
"1. Custom",
};
Menu_t main_menu = {
.title = "Main menu",
.color = BGRColorBlue,
.selected_color = BGRColorRed,
.background = BGRColorWhite,
.items_count = sizeof(items) / sizeof(items[0]),
.items = items,
};
lcd_show_menu(&lcd, &main_menu);
lcd_st7735_puts(&lcd, (LCD_Point){.x = 5, .y = 106}, "Defaulting to item");
lcd_st7735_puts(&lcd, (LCD_Point){.x = 5, .y = 118}, "0 after 3 seconds");
switch (scan_buttons(3000, BTN0)) {
case BTN0:
// Run the fractal examples.
fractal_test(&lcd);
break;
case BTN1:
lcd_st7735_puts(&lcd, (LCD_Point){.x = 5, .y = 80}, "Button 1 pressed");
timer_delay(1000);
break;
case BTN2:
break;
case BTN3:
break;
default:
break;
}
} while (1);
}
static Buttons_t scan_buttons(uint32_t timeout, Buttons_t def) {
do {
// Sample buttons (debounced).
const uint32_t in_val = read_gpio(GPIO_IN_DBNC) & 0xf;
if (in_val == 0) {
// No button pressed, so delay for 20ms and then try again, unless the timeout is reached.
const uint32_t poll_delay = 20;
timer_delay(poll_delay);
if (timeout < poll_delay) {
// Timeout reached, return default button.
return def;
} else {
// Timeout not reached yet, decrease it and try again.
timeout -= poll_delay;
}
} else {
// Some button pressed, return the sampled value.
return (Buttons_t)in_val;
}
} while (1);
}
static void fractal_test(St7735Context *lcd) {
fractal_mandelbrot_float(lcd);
timer_delay(5000);
fractal_mandelbrot_fixed(lcd);
timer_delay(5000);
}
static uint32_t spi_write(void *handle, uint8_t *data, size_t len) {
const uint32_t data_sent = len;
while (len--) {
spi_send_byte_blocking(handle, *data++);
}
while ((spi_get_status(handle) & spi_status_fifo_empty) != spi_status_fifo_empty)
;
return data_sent;
}
static uint32_t gpio_write(void *handle, bool cs, bool dc) {
set_output_bit(GPIO_OUT, LcdDcPin, dc);
set_output_bit(GPIO_OUT, LcdCsPin, cs);
return 0;
}
static void timer_delay(uint32_t ms) {
// Configure timer to trigger every 1 ms
timer_enable(50000);
uint32_t timeout = get_elapsed_time() + ms;
while (get_elapsed_time() < timeout) {
asm volatile("wfi");
}
timer_disable();
}
extended_ibex/ibex_demo_system/sw/c/demo/simpleserial-aes/CMakeLists.txt
+22
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@@ -0,0 +1,22 @@
add_definitions(-DTINYAES128C -DSS_VER=1 -DHAL_TYPE=HAL_ibex)
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../../../../vendor/newae/crypto)
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../../../../vendor/newae/hal)
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../../../../vendor/newae/simpleserial)
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../../../../vendor/newae/crypto/tiny-AES128-C)
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../../common)
add_library(simpleserial
${CMAKE_CURRENT_SOURCE_DIR}/../../../../vendor/newae/simpleserial/simpleserial.c
${CMAKE_CURRENT_SOURCE_DIR}/../../../../vendor/newae/hal/ibex/ibex_hal.c
)
add_library(tiny-AES128
${CMAKE_CURRENT_SOURCE_DIR}/../../../../vendor/newae/crypto/aes-independant.c
${CMAKE_CURRENT_SOURCE_DIR}/../../../../vendor/newae/crypto/tiny-AES128-C/aes.c
)
add_executable(simpleserial-aes ${CMAKE_CURRENT_SOURCE_DIR}/../../../../vendor/newae/simpleserial-aes/simpleserial-aes.c)
target_link_libraries(simpleserial-aes common simpleserial tiny-AES128)
extended_ibex/ibex_demo_system/sw/c/demo/simpleserial-aes/README
+18
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@@ -0,0 +1,18 @@
ChipWhisperer simpleserial-aes application, intended to be run on a
ChipWhisperer FPGA target (synth_cw305 or synth_cw312a35 targets).
This can then be used with any of the NewAE Jupyter-based courses
(https://github.com/newaetech/chipwhisperer-jupyter/tree/master/courses)
which use simpleserial-aes, with modifications to the target clock and baud
rate:
scope.clock.adc_mul = 1 # if using CW-Husky
scope.clock.adc_src = 'clkgen_x1' # if using CW-lite/pro
scope.clock.clkgen_freq = 100e6
target.baud = 115200
Note that this application (and many others!) can also be built in the
ChipWhisperer repository:
https://github.com/newaetech/chipwhisperer/tree/develop/hardware/victims/firmware/simpleserial-aes
using:
make PLATFORM=CW305_IBEX CRYPTO_TARGET=TINYAES128C
extended_ibex/ibex_demo_system/sw/c/gcc_toolchain.cmake
+7
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@@ -0,0 +1,7 @@
set(LINKER_SCRIPT "${CMAKE_CURRENT_LIST_DIR}/../common/link.ld")
set(CMAKE_SYSTEM_NAME Generic)
set(CMAKE_C_COMPILER riscv32-unknown-elf-gcc)
set(CMAKE_C_FLAGS_INIT
"-march=rv32imc -mabi=ilp32 -mcmodel=medany -Wall -fvisibility=hidden -ffreestanding")
set(CMAKE_ASM_FLAGS_INIT "-march=rv32imc")
set(CMAKE_EXE_LINKER_FLAGS_INIT "-nostartfiles -T \"${LINKER_SCRIPT}\"")
extended_ibex/ibex_demo_system/sw/common/link.ld
+113
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@@ -0,0 +1,113 @@
/* Copyright lowRISC contributors.
Licensed under the Apache License, Version 2.0, see LICENSE for details.
SPDX-License-Identifier: Apache-2.0 */
OUTPUT_ARCH(riscv)
MEMORY
{
/* 60 KiB should be enough for anybody... */
ram : ORIGIN = 0x00100000, LENGTH = 0xE000 /* 56 KiB */
stack : ORIGIN = 0x0010E000, LENGTH = 0x2000 /* 4 KiB */
}
/* Stack information variables */
_min_stack = 0x1000; /* 4K - minimum stack space to reserve */
_stack_len = LENGTH(stack);
_stack_start = ORIGIN(stack) + LENGTH(stack);
_entry_point = _vectors_start + 0x80;
ENTRY(_entry_point)
/* Rust dependency */
PROVIDE(_stext = ORIGIN(ram));
PROVIDE(_stack_start = ORIGIN(stack) + LENGTH(stack));
PROVIDE(_max_hart_id = 0);
PROVIDE(_hart_stack_size = LENGTH(stack));
PROVIDE(_heap_size = 0);
PROVIDE(UserSoft = DefaultHandler);
PROVIDE(SupervisorSoft = DefaultHandler);
PROVIDE(MachineSoft = DefaultHandler);
PROVIDE(UserTimer = DefaultHandler);
PROVIDE(SupervisorTimer = DefaultHandler);
PROVIDE(MachineTimer = DefaultHandler);
PROVIDE(UserExternal = DefaultHandler);
PROVIDE(SupervisorExternal = DefaultHandler);
PROVIDE(MachineExternal = DefaultHandler);
PROVIDE(DefaultHandler = DefaultInterruptHandler);
PROVIDE(ExceptionHandler = DefaultExceptionHandler);
PROVIDE(__pre_init = default_pre_init);
PROVIDE(_mp_hook = default_mp_hook);
PROVIDE(_start_trap = default_start_trap);
PROVIDE(_setup_interrupts = default_setup_interrupts);
SECTIONS
{
.text : {
. = ALIGN(4);
_vectors_start = .;
KEEP(*(.vectors))
_vectors_end = .;
/* Rust dependency */
KEEP(*(.init));
KEEP(*(.init.rust));
*(.text)
*(.text.*)
. = ALIGN(4);
} > ram
.rodata : {
. = ALIGN(4);
/* Small RO data before large RO data */
*(.srodata)
*(.srodata.*)
*(.rodata);
*(.rodata.*)
. = ALIGN(4);
} > ram
.data : {
. = ALIGN(4);
_sidata = LOADADDR(.data);
_sdata = .;
/* Small data before large data */
*(.sdata)
*(.sdata.*)
*(.data);
*(.data.*)
. = ALIGN(4);
_edata = .;
} > ram
.bss :
{
. = ALIGN(4);
_bss_start = .;
/* Small BSS before large BSS */
*(.sbss)
*(.sbss.*)
*(.bss)
*(.bss.*)
*(COMMON)
_bss_end = .;
. = ALIGN(4);
} > ram
/* Rust dependency */
_sbss = _bss_start;
_ebss = _bss_end;
/* ensure there is enough room for stack */
.stack (NOLOAD): {
. = ALIGN(4);
. = . + _min_stack ;
. = ALIGN(4);
stack = . ;
_stack = . ;
} > stack
}
extended_ibex/ibex_demo_system/sw/rust/.cargo/config.toml
+16
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@@ -0,0 +1,16 @@
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
[build]
target = "riscv32imc-unknown-none-elf"
[target.riscv32imc-unknown-none-elf]
runner = "../../util/load_demo_system.sh run"
rustflags = [
"-C", "link-arg=-T../common/link.ld",
]
[unstable]
build-std = ["core"]
extended_ibex/ibex_demo_system/sw/rust/Cargo.lock
Generated
+1128
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File diff suppressed because it is too large Load Diff
extended_ibex/ibex_demo_system/sw/rust/Cargo.toml
+17
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@@ -0,0 +1,17 @@
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
[workspace]
members = [
"ibex-demo-system-pac",
"ibex-demo-system-hal",
"demo/hello_world",
"demo/led",
"demo/led_hal",
"demo/lcd_hal",
"demo/pwm_hal",
]
[profile.release]
debug = true
extended_ibex/ibex_demo_system/sw/rust/README.md
+15
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@@ -0,0 +1,15 @@
# Ibex Rust stack
This a embedded Rust software stack for whom is enthusiast about Rust, embedded systems, RISC-V and open source.
## Installation
Install Rust:<https://www.rust-lang.org/tools/install>.
## Demos application
- [Hello world](demo/hello_world/README.md)
- [LED](demo/led/README.md)
## Running on the ARTY A7 FPGA
Before running, you need to build and load the bitstream to the board as described [here](../../README.md#building-fpga-bitstream).
```
cargo run --bin led
```
extended_ibex/ibex_demo_system/sw/rust/demo/hello_world/.cargo/config.toml
+7
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@@ -0,0 +1,7 @@
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
[target.riscv32imc-unknown-none-elf]
runner = "riscv32-unknown-elf-gdb -q -x gdb_init"
extended_ibex/ibex_demo_system/sw/rust/demo/hello_world/Cargo.lock
Generated
+217
View File
@@ -0,0 +1,217 @@
# This file is automatically @generated by Cargo.
# It is not intended for manual editing.
version = 3
[[package]]
name = "aho-corasick"
version = "0.7.20"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "cc936419f96fa211c1b9166887b38e5e40b19958e5b895be7c1f93adec7071ac"
dependencies = [
"memchr",
]
[[package]]
name = "bare-metal"
version = "1.0.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
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extended_ibex/ibex_demo_system/sw/rust/demo/hello_world/Cargo.toml
+16
View File
@@ -0,0 +1,16 @@
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
[package]
name = "hello_world"
version = "0.1.0"
edition = "2021"
# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
[dependencies]
panic-halt = "0.2.0"
riscv = "0.10"
riscv-rt = "0.11.0"
riscv-semihosting = {git="https://github.com/riscv-rust/riscv-semihosting", branch="master", features=["user-mode"]}
extended_ibex/ibex_demo_system/sw/rust/demo/hello_world/README.md
+26
View File
@@ -0,0 +1,26 @@
# Hello world
This demo prints a `Hello world` string to the JTAG semihosting interface.
How to run this demo:
1. Build and load a [IBEX bitstream](../../../README.md#Building-FPGA-bitstream)
2. Build and load the demo with `cargo run`.
3. Connect [openocd](../../../README.md#Debugging-an-application)
4. Run the gdb:
```console
$ riscv32-unknown-elf-gdb ../../target/riscv32imc-unknown-none-elf/debug/led
(gdb) # Connect to OpenOCD
(gdb) target remote :3333
(gdb) # Enable OpenOCD's semihosting support
(gdb) monitor arm semihosting enable
(gdb) # Flash the program
(gdb) load
(gdb) # Run the program
(gdb) continue
```
The log will show up on the openocd console (Step 3).
extended_ibex/ibex_demo_system/sw/rust/demo/hello_world/src/main.rs
+27
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@@ -0,0 +1,27 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#![no_std]
#![no_main]
extern crate panic_halt;
extern crate riscv_rt;
use core::fmt::Write;
use riscv_semihosting::hio;
use riscv_rt::entry;
#[entry]
fn main() -> ! {
// do something here
jtag_print("Hello world!").unwrap();
loop {}
}
fn jtag_print(msg: &str) -> Result<(), core::fmt::Error> {
let mut stdout = hio::hstdout().map_err(|_| core::fmt::Error)?;
writeln!(stdout, "{}", msg)?;
Ok(())
}
extended_ibex/ibex_demo_system/sw/rust/demo/lcd_hal/.cargo/config.toml
+7
View File
@@ -0,0 +1,7 @@
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
[target.riscv32imc-unknown-none-elf]
runner = "riscv32-unknown-elf-gdb -q -x gdb_init"
extended_ibex/ibex_demo_system/sw/rust/demo/lcd_hal/Cargo.toml
+21
View File
@@ -0,0 +1,21 @@
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
[package]
name = "lcd_hal"
version = "0.1.0"
edition = "2021"
# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
[dependencies]
embedded-graphics = "0.8.0"
st7735-lcd = "0.9.0"
panic-halt = "0.2.0"
riscv = {version = "0.10.1", features = ["critical-section-single-hart"]}
riscv-rt = "0.11.0"
ibex-demo-system-hal = {path = "../../ibex-demo-system-hal"}
embedded-hal = "0.2.7"
tinybmp = "0.5.0"

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