alexmr09
92 lines
2.1 KiB
Plaintext
92 lines
2.1 KiB
Plaintext
/* Copyright lowRISC contributors.
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Licensed under the Apache License, Version 2.0, see LICENSE for details.
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SPDX-License-Identifier: Apache-2.0 */
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OUTPUT_ARCH(riscv)
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/* Change this if you'd like different sizes. Arty A7-100(35) has a maximum of 607.5KB(225KB)
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BRAM space. Configuration below is for maximum BRAM capacity with Artya A7-35 while letting
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CoreMark run (.vmem of 152.8KB).
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*/
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MEMORY
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{
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ram : ORIGIN = 0x00100000, LENGTH = 0x750000
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stack : ORIGIN = 0x00850000, LENGTH = 0x200000
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}
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/* Stack information variables */
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_min_stack = 0x10000; /* 8K - minimum stack space to reserve */
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_stack_len = LENGTH(stack);
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_stack_start = ORIGIN(stack) + LENGTH(stack);
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_entry_point = _vectors_start + 0x80;
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ENTRY(_entry_point)
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/* The tohost address is used by Spike for a magic "stop me now" message. This
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is set to equal SIM_CTRL_CTRL (see simple_system_regs.h), which has that
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effect in simple_system simulations. Note that it must be 8-byte aligned.
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We don't read data back from Spike, so fromhost is set to some dummy value:
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we place it just above the top of the stack.
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*/
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tohost = 0x20008;
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fromhost = _stack_start + 0x10;
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SECTIONS
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{
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.vectors :
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{
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. = ALIGN(4);
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_vectors_start = .;
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KEEP(*(.vectors))
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_vectors_end = .;
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} > ram
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.text : {
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. = ALIGN(4);
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*(.text)
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*(.text.*)
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} > ram
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.rodata : {
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. = ALIGN(4);
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/* Small RO data before large RO data */
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*(.srodata)
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*(.srodata.*)
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*(.rodata);
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*(.rodata.*)
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} > ram
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.data : {
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. = ALIGN(4);
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/* Small data before large data */
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*(.sdata)
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*(.sdata.*)
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*(.data);
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*(.data.*)
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} > ram
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.bss :
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{
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. = ALIGN(4);
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_bss_start = .;
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/* Small BSS before large BSS */
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*(.sbss)
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*(.sbss.*)
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*(.bss)
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*(.bss.*)
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*(COMMON)
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_bss_end = .;
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} > ram
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/* ensure there is enough room for stack */
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.stack (NOLOAD): {
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. = ALIGN(4);
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. = . + _min_stack ;
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. = ALIGN(4);
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stack = . ;
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_stack = . ;
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} > stack
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}
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